SN74LS90D - Decade Counter, 4-Bit, LS-TTL, 14-SOIC | Texas Instruments
N.º de pieza: SN74LS90D ✓ Activo| Cant. | Precio unitario | Total |
|---|---|---|
| 1 | $1.45 | $1,45 |
| 10 | $1.2 | $12,00 |
| 100 | $0.95 | $95,00 |
| 500 | $0.78 | $390,00 |
| 1.000 | $0.65 | $650,00 |
SN74LS90D Descripción general
A decade counter is a fundamental sequential-logic building block in digital electronics. Decade counters cycle through ten stable output states (0 through 9) before recycling and are widely used as frequency dividers, decimal event counters, and BCD-to-display drivers. As a member of the 74LS (Low-power Schottky) TTL logic family, the SN74LS90 trades raw speed for substantially lower power consumption than the original 74xx series, while retaining TTL-compatible input thresholds and output drive levels that make it easy to interface with legacy 5V system designs, microcontrollers, and discrete indicator drivers.
Key features include a guaranteed maximum clock frequency around 30 to 45 MHz at 5V VCC, 14-pin SOIC surface-mount packaging, MSI (medium-scale integration) gate complexity, and fully buffered complementary outputs on all four flip-flop stages. The part operates from a single 4.75V to 5.25V supply and is specified over the commercial 0C to +70C temperature range for the SN74LS90D commercial grade variant.
Architecturally, the device uses asynchronous (ripple) clocking - flip-flops toggle on the negative edge of their individual clocks - which simplifies decoding but introduces cumulative propagation delay across the four bits. Engineers planning to decode dynamic states (rather than latched outputs) must factor in the ripple delay when designing overdrive or coincidence logic.
Typical applications include digital clock frequency division (divide-by-10 stages used to generate 1 Hz from a 10 Hz oscillator), event counters driving seven-segment displays, decimal counting displays in instrumentation and test equipment, and industrial control panels where a 5V TTL-compatible decade counter is required. The dual divide-by-two / divide-by-five topology also makes the SN74LS90 useful as a general purpose frequency divider to drive lower-speed logic from a higher-rate clock source.
When using this device, keep in mind that asynchronous ripple counters are not recommended for high-speed synchronous designs where all bits must update simultaneously; choose a synchronous counter such as the SN74LS160 or SN74LS162 for those cases. Decoupling VCC with a 0.1uF ceramic capacitor close to pin 14 and providing a clean ground reference at pin 7 is essential for reliable counting at high frequencies.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet. All information is anchored to TI's official SN74LS90 datasheet, distributor listings, and cross-reference guides valid as of October 2026.
Alternativas directas para SN74LS90D — mismo encapsulado, compatible pin a pin. Se excluyen las piezas de otro encapsulado que requieren retrabajo de la PCB.
Herramienta de comparación rápida — seleccione piezas alternativas para compararlas lado a lado:
SN74LS90DR
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
SN74LS90DG4
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
SN74LS90NE4
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
SN74LS90DRG4
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
SN74LS90DR2G
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
SN74LS90D Valores máximos y características eléctricas
| Función | Decade / divide-by-12 / 4-bit binary counter |
| Counter Type | Asynchronous (ripple), negative-edge triggered |
| Number of Elements | 1 |
| Bits per Element | 4 |
| Logic Family | LS-TTL (74LS series) |
| Technology | Low-power Schottky TTL |
| Supply Voltage VCC | 4.75 V to 5.25 V |
| Temperatura de funcionamiento | 0 C to +70 C (commercial) |
| Encapsulado | 14-SOIC (D) |
| Número de pines | 14 |
| Tipo de montaje | Surface Mount |
| Output Drive | LS-TTL standard (fan-out per datasheet) |
| Reset Inputs | Yes (asynchronous, RO(1) and RO(2)) |
| Estado RoHS | Compliant (per TI product page) |
| Lead Free | Yes |
Configuración de pines de SN74LS90D
| Pin 1 | CKB — Clock input B (divide-by-5 section) |
| Pin 2 | R0(1) — Reset input 1 (active high) |
| Pin 3 | R0(2) — Reset input 2 (active high) |
| Pin 4 | NC — Not connected (per datasheet) |
| Pin 5 | VCC — Power supply (+5 V) |
| Pin 6 | GND — Ground |
| Pin 7 | NC — Not connected (per datasheet) |
| Pin 8 | QD — Counter output bit D (MSB) |
| Pin 9 | QC — Counter output bit C |
| Pin 10 | GND — Ground |
| Pin 11 | QB — Counter output bit B |
| Pin 12 | QA — Counter output bit A (LSB) |
| Pin 13 | NC — Not connected (per datasheet) |
| Pin 14 | CKA — Clock input A (divide-by-2 section) |
Aplicaciones típicas
SN74LS90D es adecuado para 6 aplicacións: Digital Clock Frequency Divider, BCD Event Counter with Seven-Segment Display, Frequency Divider Chain for Synthesizer / PLL Reference, Industrial Decade Counters and Batch Controllers, Divide-by-12 and Bi-Quinary Timing Stages, Logic Design Trainer and TTL Lab Bench Counter.
Digital Clock Frequency Divider
The SN74LS90D's divide-by-10 topology is the classic building block for deriving 1 Hz from a 10 Hz oscillator stage in digital wall clocks and timer displays. Cascading two SN74LS90D parts produces a divide-by-100 stage, and three stages deliver divide-by-1000 (Hz-from-kHz), letting engineers build accurate time references from simple crystal or RC oscillators. The 14-SOIC package keeps the counter compact on the clock PCB while the LS-TTL 5V supply matches typical clock-controller IC rails. Designers should follow the TI datasheet connection diagram for BCD mode (QA to clock-B) to ensure clean division without glitches on the transition between 9 and 0.
Recomendado
BCD Event Counter with Seven-Segment Display
Pair the SN74LS90D with a BCD-to-seven-segment decoder such as the SN74LS47D or SN74LS48D to drive a multiplexed decimal display for instrumentation, test equipment, or production-line counters. The counter's QA-QD outputs deliver standard 8421 BCD that the decoder converts to the seven-segment pattern; multiple cascaded SN74LS90D stages then display three- or four-digit decimal counts. Because the SN74LS90D is asynchronous, decoded outputs may show transient spikes during transitions and a latch such as the SN74LS373 can be added after the counter if clean readouts are needed.
Recomendado
Frequency Divider Chain for Synthesizer / PLL Reference
In PLL and frequency-synthesizer designs, the SN74LS90D serves as a coarse divide-by-10 prescaler to bring a high-frequency reference (such as 10 MHz or 1 MHz) into the input range of a programmable divider or phase detector. Its LS-TTL input thresholds are compatible with 5V crystal-oscillator outputs, and the dual divide-by-2 / divide-by-5 architecture lets the designer tap either side for additional tap points (divide-by-2, divide-by-5, or divide-by-10). For best phase-noise performance, run VCC through a dedicated low-noise LDO and place a 0.1uF ceramic bypass capacitor close to pin 14.
Recomendado
Industrial Decade Counters and Batch Controllers
Industrial batch-counters, lot tracers, and event-totalizers frequently use the SN74LS90D as a unit-decade counter that increments on each sensor pulse and latches into a BCD display. Because the part operates over the commercial 0C to +70C range and runs from a robust 5V TTL rail, it tolerates the electrical noise of factory floors when paired with proper input filtering and optocoupler isolation on the count input. Its two asynchronous reset inputs (R0(1) and R0(2)) make hardware reset of the count trivial when an operator presses a button.
Recomendado
Divide-by-12 and Bi-Quinary Timing Stages
Beyond its decade mode, the SN74LS90D can be wired as a divide-by-12 counter or as a symmetrical bi-quinary (5-2) divide-by-10 counter per the TI SN74LS90 datasheet. These modes are useful in timing circuits where the count sequence must be optimized for downstream decoder logic, or where a symmetric 50/50 output (bi-quinary) is preferred over the BCD-style asymmetric waveform. Designers selecting bi-quinary mode should connect QD back to the A-clock input per the datasheet's bi-quinary connection diagram, and note that the QA output then provides the symmetric 50/50 divided clock.
Recomendado
Logic Design Trainer and TTL Lab Bench Counter
Because the SN74LS90D is a textbook MSI counter, it is a staple on university logic-design lab benches and hobbyist TTL workbenches. Students wire it up with 555-timer clocks, debounced push-buttons, and seven-segment boards to visualize asynchronous counting, propagation delay, and decoder propagation. Its low cost, wide availability, and benign 5V supply make the SN74LS90D a forgiving educational part that still teaches the real-world timing concerns engineers face in production designs.
Recomendado
Resumen de productos recomendados
Datos de referencia de ingeniería para SN74LS90D — comparación, orientación de diseño e información de cumplimiento.
Guía de selección
Comparación con alternativas
| Parámetro | Este producto | SN74LS90DR | SN74LS90DG4 | SN74LS90DRG4 | SN74LS90DR2G |
|---|---|---|---|---|---|
| Package | 14-SOIC (D) | 14-SOIC (D) - same | 14-SOIC (D) - same | 14-SOIC (D) - same | 14-SOIC (D) - same (onsemi) |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | onsemi |
| Function | Decade counter | Decade counter | Decade counter | Decade counter | Decade counter |
| Logic Family | 74LS (LS-TTL) | 74LS (LS-TTL) | 74LS (LS-TTL) | 74LS (LS-TTL) | 74LS (LS-TTL) |
| Supply Voltage | 4.75V to 5.25V | 4.75V to 5.25V | 4.75V to 5.25V | 4.75V to 5.25V | 4.75V to 5.25V |
| Operating Temperature | 0C to +70C | 0C to +70C | 0C to +70C | 0C to +70C | 0C to +70C |
| RoHS Status | Compliant (D suffix is non-green on early lots - confirm per reel) | Compliant (R suffix tape/reel) | Compliant (G4 = green) | Compliant (green + tape/reel) | Compliant (onsemi) |
| Single-Unit Price (USD, as of 2026-10-22) | ~$1.45 | ~$1.45 | ~$1.45 | ~$1.45 | ~$1.30 (onsemi) |
Diferenciadores clave
- Dual divide-by-2/divide-by-5 topology in a single 14-SOIC package (frente a SN74LS93D)
- Cross-brand second source available from onsemi (frente a SN74LS90DR2G (onsemi))
- Asynchronous reset inputs simplify batch-controller wiring (frente a SN74LS160D)
Notas de diseño
The SN74LS90D draws a quiescent supply current in the low-mA range (per LS-TTL family specs), but when fully switching at high count rates the average I CC rises sharply and can approach 20-40 mA. Provide a stable 5V rail with a 0.1uF ceramic bypass capacitor placed within 5mm of pin 5 (VCC) to keep ripple low. For mixed logic boards, isolate the LS-TTL supply from noisy MCU rails with a small ferrite bead or dedicated LDO when the SN74LS90D sits next to a switching regulator.
SN74LS90D is an asynchronous (ripple) counter, meaning flip-flops are clocked in series and outputs do not change in true simultaneous fashion. Cumulative propagation delay through the four bits can reach tens of nanoseconds, so dynamic decoding of intermediate counts may produce transient 'glitch' patterns. If clean decoded outputs are required (e.g., to drive a display decoder during transitions), add a transparent latch such as the SN74LS373 after the counter and strobe it once the ripple has settled (typically after t_pd_max).
When wiring the SN74LS90D into decade (BCD) mode, ensure that QA (pin 12) is connected to the CKB input (pin 1), and the input clock drives CKA (pin 14) - reverse wiring will not count in decimal. The two reset pins R0(1) (pin 2) and R0(2) (pin 6) must both be held LOW for normal counting; if either is left floating, the counter may randomly reset. Pull both reset pins to GND through a 10k resistor or drive them actively with your reset logic.
Keep the 14-SOIC footprint compact and route count-clock traces with controlled impedance and short stubs to minimize reflections at high clock rates. Place the VCC bypass capacitor and an optional bulk 1-10uF capacitor as close as possible to the IC. If you are cascading multiple SN74LS90D chips, keep QA-to-CKB traces short and shielded (or guarded with ground) to avoid false clocking of the next stage.
Información de cumplimiento
Per TI SN74LS90 product page and onsemi SN74LS90DR2G product page - RoHS and REACH compliant, Pb-free, manufactured in compliance with conflict-mineral regulations. Commercial 0C to +70C grade only; not AEC-Q100 qualified - choose an automotive-grade TTL part such as SN74LS90-Q1 from TI for vehicle applications.
