TPS546B24ARVFR - 18V, 20A Stackable Sync Buck Converter | TI
N.º de pieza: TPS546B24ARVFR ✓ Activo| Cant. | Precio unitario | Total |
|---|---|---|
| 1 | $8.95 | $8,95 |
| 10 | $8.06 | $80,60 |
| 100 | $7.16 | $716,00 |
| 500 | $6.45 | $3.225,00 |
| 1.000 | $5.74 | $5.740,00 |
| 2.500 | $5.2 | $13.000,00 |
TPS546B24ARVFR Descripción general
A buck converter (also called a step-down switching regulator) is a type of DC-DC converter that uses an LC low-pass filter and high-frequency switching to deliver a lower regulated output voltage from a higher input rail with high efficiency. The synchronous topology replaces the traditional Schottky rectifier with a low-side MOSFET to reduce conduction loss, while SWIFT (TI's brand for high-current, fast-transient buck converters) emphasizes small footprint and telemetry features for distributed power systems. This category sits within Power Management > Voltage Regulators > DC-DC Converters, serving as the workhorse building block that converts a 12-V or 18-V bus into the sub-5-V rails needed by FPGAs, ASICs, and processors.
Key features include selectable switching frequency from 225 kHz to 1.5 MHz via PMBus or pin-strap, 0.6-V reference with 1% output accuracy, adaptive voltage scaling, and comprehensive fault telemetry including output current, voltage, and temperature read-back through PMBus. The 40-pin LQFN-CLIP package provides top-side cooling with 0.9 mm height and a thermal pad for low thermal resistance, while PMBus commands enable margining, sequencing, and fault logging.
The architecture combines a peak-current-mode inner loop with an average-current-mode outer loop to simplify parallel/stackable operation - critical for high-current rails where two or four phases must share load precisely. Pin-strap configuration lets the designer set switching frequency, soft-start, and current-sharing mode without software, simplifying boot-up before the system controller initializes the PMBus.
Typical applications include powering high-performance FPGAs, ASICs, processors, and DDR memory in telecom/datacenter equipment, industrial automation controllers, and 12-V distributed-bus systems. The 20-A single-channel capability also suits single-rail SoC designs in networking switches and baseband cards.
Design considerations: ensure sufficient input/output ceramic capacitance per datasheet Section 7.4, provide a Kelvin-sense ground return for the PGND, and choose switching frequency to trade off efficiency against EMI margin. This page synthesizes distributor pricing, drop-in alternatives, and PCB layout guidance not found in the manufacturer datasheet.
Alternativas directas para TPS546B24ARVFR — mismo encapsulado, compatible pin a pin. Se excluyen las piezas de otro encapsulado que requieren retrabajo de la PCB.
Variantes de esta serie
Modelos de la misma serie compatibles directamente con TPS546B24ARVFR (mismo factor de forma y huella) — difiere en Continuous Output Current, Control Mode, Digital Interface, Output Voltage Range, Package.
Herramienta de comparación rápida — seleccione piezas alternativas para compararlas lado a lado:
TPS546B24ARVFT
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
TPS546B24ARVFR-Q1
✅ Sustitución directa ⚠️ Especificaciones sin verificar📋 Alternativa de referencia (no en el catálogo)
TPS546D24ARVFR
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
TPS546A24ARVFR
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
TPS544B25RVFR
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
TPS546B24ARVFR Valores máximos y características eléctricas
| Topología | Synchronous Buck (Step-Down) |
| Input Voltage (PVIN/AVIN) | 2.95 V to 18 V |
| Rango de tensión de salida | 0.6 V to 5.5 V (adjustable) |
| Continuous Output Current | 20 A |
| Stackable Configuration | 2x / 3x / 4x with current sharing |
| Switching Frequency Range | 225 kHz to 1.5 MHz (selectable via PMBus or pin-strap) |
| High-Side MOSFET Rds(on) | 5.5 mΩ |
| Low-Side MOSFET Rds(on) | 1.8 mΩ |
| Control Mode | Average current mode with selectable internal compensation |
| Digital Interface | PMBus (voltage, current, temperature telemetry; margining; sequencing) |
| Output Voltage Reference | 0.6 V ±1% |
| Temperatura de unión de funcionamiento | -40 °C to +150 °C |
| Encapsulado | LQFN-CLIP-40 (RVF), 7 mm x 5 mm, 0.9 mm height |
| Tipo de montaje | Surface Mount |
| Estado RoHS | Compliant |
Configuración de pines de TPS546B24ARVFR
| Pin 1 | AGND — Analog ground return for internal references and PMBus logic |
| Pin 2 | AVIN — Analog input supply (2.95 V to 18 V); powers internal LDO and analog circuits |
| Pin 3 | EN/UVLO — Enable and undervoltage lockout programming pin |
| Pin 4 | PGOOD — Power good open-drain output; pulls low on fault |
| Pin 5 | MSEL1 — Pin-strap mode select 1 (selects switching frequency and current-share mode) |
| Pin 6 | MSEL2 — Pin-strap mode select 2 |
| Pin 7 | RT/CLK — Resistor timing / external clock input for switching frequency |
| Pin 8 | COMP — External compensation node for average current mode loop |
| Pin 9 | FB — Voltage feedback; connect to VOUT resistor divider |
| Pin 10 | VREF — 0.6 V internal reference; bypass with 100 nF |
| Pin 11 | SCL — PMBus serial clock input |
| Pin 12 | SDA — PMBus serial data (bidirectional) |
| Pin 13 | ALERT — PMBus ALERT open-drain output |
| Pin 14 | DGND — Digital ground return for PMBus |
| Pin 15 | SHARE — Current-share bus; tie to other TPS546B24A devices for parallel operation |
| Pin 16 | NC — Not connected (per datasheet) |
| Pin 17 | NC — Not connected (per datasheet) |
| Pin 18 | BOOT — Bootstrap supply for high-side gate driver |
| Pin 19 | PH — Phase node (switching node) - connect to output inductor |
| Pin 20 | PH — Phase node (switching node) - connect to output inductor |
| Pin 21 | PH — Phase node (switching node) - connect to output inductor |
| Pin 22 | PH — Phase node (switching node) - connect to output inductor |
| Pin 23 | PH — Phase node (switching node) - connect to output inductor |
| Pin 24 | VOUT — Output voltage sense (used for current sense and telemetry) |
| Pin 25 | VOUT — Output voltage sense (used for current sense and telemetry) |
| Pin 26 | VSNS — Voltage sense differential + |
| Pin 27 | VSNS- — Voltage sense differential - |
| Pin 28 | PGND — Power ground return for low-side MOSFET |
| Pin 29 | PGND — Power ground return for low-side MOSFET |
| Pin 30 | PGND — Power ground return for low-side MOSFET |
| Pin 31 | PGND — Power ground return for low-side MOSFET |
| Pin 32 | PGND — Power ground return for low-side MOSFET |
| Pin 33 | PGND — Power ground return for low-side MOSFET |
| Pin 34 | PVIN — Power input supply (2.95 V to 18 V) for high-side MOSFET |
| Pin 35 | PVIN — Power input supply (2.95 V to 18 V) for high-side MOSFET |
| Pin 36 | PVIN — Power input supply (2.95 V to 18 V) for high-side MOSFET |
| Pin 37 | PVIN — Power input supply (2.95 V to 18 V) for high-side MOSFET |
| Pin 38 | PVIN — Power input supply (2.95 V to 18 V) for high-side MOSFET |
| Pin 39 | PVIN — Power input supply (2.95 V to 18 V) for high-side MOSFET |
| Pin 40 | EPAD — Exposed thermal pad (PGND); solder to PCB for low thermal resistance |
Aplicaciones típicas
TPS546B24ARVFR es adecuado para 6 aplicacións: FPGA Core Rail Power, ASIC/SoC Processor Power, DDR Memory VTT Termination, Telecom and Networking Switch Power, Industrial 24-V Bus Step-Down, Datacenter 48-V to Point-of-Load Conversion.
FPGA Core Rail Power
The TPS546B24ARVFR's 20 A continuous output and 0.6-V ±1% reference make it ideal for powering FPGA core rails such as Xilinx Kintex-7 or Intel Cyclone 10 GX. With adaptive voltage scaling via PMBus AVS commands, the device supports dynamic core voltage changes for power-saving modes, while the 5.5 mΩ / 1.8 mΩ integrated MOSFETs deliver above 90% efficiency at 12-V to 1.0-V conversion under 10-A load. A 1.0 uH inductor and 4 x 22 uF ceramic input capacitors provide a compact two-layer solution under 100 mm².
Recomendado
ASIC/SoC Processor Power
For ASIC and SoC designs requiring 15-20 A core current at 0.85 V to 1.2 V, the TPS546B24ARVFR's 225 kHz to 1.5 MHz selectable switching and PMBus margining provide full observability and trim of the core rail. The wide 2.95 V to 18 V input range covers both 5-V and 12-V intermediate bus rails, eliminating the need for an upstream pre-regulator. Stack two devices for 40 A on high-core-count SoCs with current-share accuracy below 5%.
Recomendado
DDR Memory VTT Termination
The TPS546B24ARVFR can deliver the high transient currents required by DDR4/DDR5 VTT termination rails during read/write cycles. Selecting 1.5 MHz switching through PMBus shrinks the inductor to 0.47 uH, fitting the VTT termination into a compact footprint below 50 mm². Average current mode control with selectable internal compensation eliminates the need for external loop compensation components, simplifying the BOM. Add TPS3808G50QDBVRQ1 for supply voltage supervision.
Recomendado
Telecom and Networking Switch Power
The 18-V input tolerance of TPS546B24ARVFR suits 12-V telecom bus architectures that may see 16-V transient surges per ETSI EN 300 132-2. PMBus telemetry of output current and junction temperature supports predictive maintenance in carrier-grade Ethernet switches, while the 0.9 mm package height fits slim 1U line-card profiles. Stack 2x for 40 A on switching ASIC rails, with stacking current-share accuracy that meets InfiniBand-style load transient requirements.
Recomendado
Industrial 24-V Bus Step-Down
In 24-V industrial bus systems (with transients up to 36 V), the TPS546B24ARVFR should be paired with an upstream protection device such as TPS25942ARVCT for hot-swap and over-voltage clamping. After the protection stage, the B24A steps the bus down to 5 V or 3.3 V for PLC and motor-drive control electronics, leveraging the 18-V continuous input limit plus the protection device's foldback. Industrial temperature grade supports -40 °C to +125 °C ambient operation.
Recomendado
Datacenter 48-V to Point-of-Load Conversion
In datacenter 48-V intermediate bus architectures, the TPS546B24ARVFR typically follows a first-stage isolation converter (such as the TPS54560QDDAQ1) that steps 48 V to 12 V. The B24A then converts 12 V to 0.85 V to 3.3 V point-of-load rails for high-performance CPUs and memory. PMBus telemetry streams current and voltage data back to the BMC for power budgeting enforcement, and 2x/3x/4x stacking supports CPU core rails above 60 A without changing the board layout.
Recomendado
Resumen de productos recomendados
Datos de referencia de ingeniería para TPS546B24ARVFR — comparación, orientación de diseño e información de cumplimiento.
Guía de selección
Comparación con alternativas
| Parámetro | Este producto | TPS546B24ARVFT | TPS546B24ARVFR-Q1 | TPS546D24ARVFR | TPS546A24ARVFR | TPS544B25RVFR |
|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | LQFN-CLIP-40 (RVF) | LQFN-CLIP-40 (RVF) - same | LQFN-CLIP-40 (RVF) - same | LQFN-CLIP-40 (RVF) - same | LQFN-CLIP-40 (RVF) - same | LQFN-CLIP-40 (RVF) - same |
| PMBus Interface | Yes | Yes | Yes | Yes | Yes | Yes (per ETEI) |
Diferenciadores clave
- Stackable 2x/3x/4x current-share up to 80 A (frente a TPS546A24ARVFR)
- Wide 18-V input tolerance for industrial 12-V bus surge margin (frente a TPS546D24ARVFR)
- Automotive-grade option available in same footprint (frente a TPS546B24ARVFR-Q1)
Notas de diseño
Estimated: input ceramic capacitor bank of 4 x 22 uF X7R in 0805 placed within 5 mm of PVIN pins is required to keep input ripple below 50 mV at 20 A load. Use a single PGND copper pour under the package that ties directly to the system ground plane through a low-impedance via array (at least 9 vias of 0.3 mm diameter) under the exposed thermal pad. According to the TI datasheet Section 7.4, this layout keeps the high-frequency switching current loop area below 100 mm² to minimize EMI.
Estimated: at VIN = 12 V, VOUT = 1.0 V, IOUT = 20 A, and FSW = 500 kHz, the TPS546B24ARVFR dissipates roughly 3-4 W (assuming 92% efficiency). With the LQFN-CLIP-40 package's copper-clip thermal pad and a 1-oz 4-layer PCB thermal via array, theta_JA falls below 15 °C/W, keeping junction rise under 60 °C above ambient. For continuous 20 A operation at +85 °C ambient, top-side airflow of 100 LFM is recommended to stay below the 150 °C junction limit.
Common pitfall: routing the PMBus SCL and SDA traces over PH (phase) copper pour causes logic glitches from capacitive coupling. Keep PMBus traces on an inner layer or route them on the top layer directly over a continuous DGND pour, with at least 0.2 mm spacing to any PH copper. According to the TI datasheet, the SHARE pin must be left floating on a single (non-stacked) device; tying it to ground or to another device's SHARE on a single-channel design disables the internal reference and prevents startup.
Información de cumplimiento
RoHS compliant per TI product page. Standard part is not AEC-Q100 qualified; choose TPS546B24ARVFR-Q1 for automotive. REACH compliance per EU database. Halogen-free status not stated in provided web data and marked unknown.
