ADC/DAC
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LTC2151IUJ-12 - 12-Bit 210Msps ADC, 40-QFN | Analog Devices
The Analog Devices LTC2151IUJ-12 is a single-channel 12-bit pipelined analog-to-digital converter (ADC) sampling at 210 Msps, packaged in a 40-lead 6mm x 6mm QFN (UJ suffix) with an exposed thermal pad. It is part of the LTC2152-12/LTC2151-12/LTC2150-12 pin-compatible ADC family, designed for digitizing high-frequency, wide-dynamic-range signals in communications, instrumentation, and defense imaging systems. A pipelined ADC is a high-speed converter architecture that processes the analog input through multiple low-resolution stages in parallel, each stage producing a sub-ADC residue that is digitized by the next stage. This approach enables sample rates well above what successive-approximation architectures can achieve, while maintaining low latency and good spurious-free dynamic range (SFDR). The LTC2151-12 sits at the top of the signal-chain hierarchy: analog sensor -> anti-alias filter -> pipelined ADC -> FPGA/ASIC digital processing. Key features include 1.25 GHz full-power bandwidth sample-and-hold, an optional clock duty-cycle stabilizer for jitter-insensitive operation, and low-power Sleep and Nap modes that reduce dissipation when the converter is idle. The serial SPI port allows in-system configuration of output format, gain, offset, and channel modes. Pin-compatible 14-bit versions (LTC2251-14 family) allow system scalability by swapping the ADC without PCB rework. The device accepts differential or single-ended analog inputs and produces LVDS, parallel CMOS, or serialized LVDS outputs selectable via SPI, simplifying interface to FPGAs. Excellent AC performance with high SFDR makes the LTC2151-12 suitable for directly digitizing IF signals in software-defined radio and radar receivers where spurious content can mask weak targets. Typical applications include cellular base-station receivers, radar and electronic-warfare signal processing, medical imaging front-ends, and high-speed data acquisition cards. The wide input bandwidth permits undersampling of IF carriers, reducing system cost by eliminating a downconversion stage. When designing with this ADC, ensure the analog input network presents 50 ohm (or 200 ohm differential) termination and that the encode clock source has low jitter (<200 fs RMS) to preserve SNR at high input frequencies. The exposed pad must be soldered to a continuous ground plane for thermal and electrical performance. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, including parametric cross-reference guidance for engineers migrating between the 12-bit and 14-bit LTC215x family members.
LTC2152IUJ-12 - 12-Bit 250Msps ADC, Single 1.8V Supply, 40-QFN | Analog Devices
The Analog Devices LTC2152IUJ-12 is a single-channel 12-bit analog-to-digital converter (ADC) sampling at up to 250 Msps, housed in a 40-lead 6x6 mm QFN package (UJ suffix). It is one of three speed grades in the LTC215x-12 family, alongside the 210 Msps LTC2151-12 and the 170 Msps LTC2150-12, and operates from a single 1.8 V analog supply with a separate 1.8 V digital supply for low-noise mixed-signal integration. An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that samples continuous-time analog voltages at discrete instants and quantises them into binary codes; pipeline ADCs such as the LTC2152-12 use a multi-stage switched-capacitor architecture that delivers high sample rates while preserving resolution. The LTC2152-12 belongs to the category hierarchy: ADC -> data converter -> mixed-signal IC -> semiconductor, serving communications, instrumentation, and defence systems that demand wide-bandwidth, high-dynamic-range signal acquisition. Key differentiating specifications include 12-bit resolution at 250 Msps real sampling rate, 1.8 V single supply operation, an internal high-bandwidth track-and-hold, differential analog inputs (per datasheet, the inputs must be driven differentially for specified performance), CMOS or DDR LVDS digital-output modes selectable per application, and a low-jitter clock PLL that relaxes the front-end analog filter requirements. The 40-QFN (6x6) package integrates an exposed pad that anchors the thermal and grounding strategy. Architecture-wise, the converter uses a pipelined core with digital error correction across multiple 1.5-bit-per-stage sub-ADCs, weighted against a precision reference and reconstructed by a latency-corrected output stage; this approach delivers spurious-free dynamic range (SFDR) suitable for multi-carrier wireless basestations and pulsed radar receivers where spurious content must remain well below the wanted signal. Typical applications include wideband digitisation of IF/RF signals in wireless infrastructure, digital oscilloscopes and spectrum analysers, radar and electronic-warfare receivers, cable-headend DOCSIS upstream capture, and medical ultrasound beamforming front-ends. The -IUJ suffix indicates the industrial temperature range (-40C to +85C) per ADI's part-numbering convention. When designing with this part, follow ADI's recommended differential input drive network (balun or transformer-coupled op-amp), place the analog and digital 1.8 V rails on separate PCB planes with a ferrite bead between them, and expose the bottom-side thermal pad with adequate vias to a ground pour - the package lead frame cannot dissipate the converter's full-load power without this copper area. This page synthesises ADI datasheet extracts, distributor pricing as of 2026-10-13, and a drop-in alternatives list not found on a single distributor page, giving engineers a faster cross-package/parametric path than re-querying DigiKey or Mouser manually.
LTC2152IUJ-14 - 14-Bit 250Msps ADC, 40-QFN | Analog Devices
The Analog Devices LTC2152IUJ-14 is a 14-bit, 250 Msps single-channel pipelined analog-to-digital converter (ADC) housed in a 40-lead QFN (6 mm x 6 mm) package with an exposed pad for thermal dissipation. Per the LTC2152-14 family datasheet (21521014fa), it features ±0.85 LSB INL (typical), ±0.25 LSB DNL (typical), no missing codes over temperature, and 1.82 LSBRMS transition noise, providing accurate conversion for high-speed signal acquisition. The wideband input supports a 1.4 GHz analog front-end, enabling excellent spurious-free dynamic range at high intermediate frequencies for communications and instrumentation front ends. DDR LVDS digital outputs simplify FPGA/ASIC interface alignment, while the differential ENC+/ENC- sample clock accepts sine, PECL, LVDS, TTL, or CMOS drive levels and an optional clock duty-cycle stabilizer preserves SNR across non-50% duty clocks. Industrial temperature grade (-40°C to +85°C) and a precision internal reference make the LTC2152IUJ-14 well-suited to demanding IF sampling, LTE/WiMAX base stations, and multi-carrier software-defined radio platforms. Common applications also include medical imaging, radar/LIDAR digitizers, and high-end test/measurement digitizer boards where the wide input bandwidth and low latency (six clock cycles) maximize usable signal headroom. At 250 Msps, typical power consumption allows fanless operation with adequate PCB copper on the exposed pad. According to the manufacturer datasheet, the LTC2152IUJ-14 is pin-compatible with the LTC2150-14 (170 Msps) and LTC2151-14 (210 Msps) in the same 40-QFN, giving designers a clear migration path when system sample-rate requirements change late in development. The industrial temperature grade ("I" suffix) and lead-free ("PBF") designation also qualify the part for harsh-environment embedded and ruggedized platforms. This page synthesizes distributor pricing, drop-in same-package alternatives (LTC2150/LTC2151 family), and practical PCB/layout guidance not found in the manufacturer datasheet alone.
LTC2155CUP-12 - Dual 12-Bit 170Msps ADC | Analog Devices
The Analog Devices LTC2155CUP-12 is a dual 12-bit 170 Msps analog-to-digital converter (ADC) designed for digitizing high-frequency, wide dynamic range signals. Housed in a 64-lead QFN (9 mm × 9 mm) package, the LTC2155CUP-12 delivers 68.5 dB SNR and 90 dB SFDR, while consuming only 545 mW total from a single 1.8 V supply. The device supports a single 1.8 V supply with DDR LVDS outputs and an easy-to-drive 1.5 V peak-to-peak input range. What is a pipelined ADC? A pipelined analog-to-digital converter is a high-speed ADC architecture that breaks the conversion into multiple low-resolution stages, each handling one sample per clock cycle. This pipeline approach enables high sampling rates (hundreds of Msps) while maintaining moderate resolution (10-16 bits), making pipelined ADCs the standard for communications, radar, and instrumentation applications. The LTC2155 belongs to the dual-pipelined ADC category, integrating two matched ADC channels on a single die for I/Q baseband or diversity reception. Key features of the LTC2155CUP-12 include a 1.25 GHz full-power bandwidth sample-and-hold, an optional clock duty cycle stabilizer, low-power sleep and nap modes, and a serial SPI port for configuration. The pin-compatible 14-bit versions (LTC2157-14/LTC2156-14/LTC2155-14) allow easy migration when higher dynamic range is needed. The differential inputs are easy to drive, simplifying front-end design for direct-IF sampling receivers. The architecture uses a high-speed pipelined core with on-chip reference and sample-and-hold, achieving excellent linearity and low jitter. DDR LVDS outputs simplify data capture by providing one data pair per channel per clock edge, reducing the number of data lines routed on the PCB. The internal duty cycle stabilizer compensates for clock source imperfections, preserving SNR at high input frequencies. Typical applications include communications receivers, cellular base stations, radar and LiDAR signal chains, portable instrumentation, medical imaging front-ends, and software-defined radio (SDR) platforms. The combination of dual channels, low power, and small QFN-64 footprint makes the LTC2155CUP-12 particularly suited to multi-channel compact systems. When designing with this ADC, pay close attention to the analog input network: a differential transformer or driver amplifier must present 1.5 V peak-to-peak to maximize SNR. Use low-jitter clock sources and matched-length differential output pairs to preserve LVDS timing margins at 170 Msps. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone.
LTC2155CUP-14 - Dual 14-Bit 170Msps ADC | Analog Devices
The Analog Devices LTC2155CUP-14 is a dual-channel, 14-bit, 170 Msps pipelined analog-to-digital converter housed in a 64-pin QFN (9x9 mm) package. It integrates two simultaneously-sampling ADC channels with parallel CMOS outputs, supports differential inputs, and operates from a 1.7 V to 1.9 V analog supply, drawing approximately 1.0 W per pair of channels at full sample rate. An ADC (Analog-to-Digital Converter) is a data converter IC that transforms continuous analog signals into discrete digital codes for processing by FPGAs, ASICs, DSPs or microcontrollers. Within the converter hierarchy, the LTC2155CUP-14 sits in the high-speed pipelined sub-family, which is the architecture of choice for communications, radar, instrumentation, and defense applications where tens-to-hundreds of Msps are required with 12-16 bit resolution. Pipelined ADCs use a multi-stage switched-capacitor architecture with per-stage residue amplifiers and digital error correction, achieving high sample rates at moderate power while maintaining low latency suitable for many baseband and IF signal chains. Key specifications include 14-bit resolution, 170 Msps sampling rate per channel, 70.1 dB SNR (with 100 MHz input) and 88 dB SFDR, plus a 1.4 GHz analog input bandwidth. The part supports both DDR (Double Data Rate) CMOS and DDR LVDS output modes, and accepts differential analog inputs, enabling direct interface to differential IF chains without external gain blocks. Internal PLL/VCO and clock duty-cycle stabilizer simplify board-level clocking, and per-channel gain/offset adjustment is supported via SPI. Typical applications include broadband communications receivers, LTE/4G base-station digitizers, software-defined radio (SDR), radar and electronic-warfare IF sampling, medical imaging front-ends, and high-speed data acquisition cards for test and measurement. Differential input topology and selectable output modes also simplify interface to Altera/Xilinx FPGAs and high-speed ASICs. When designing with the LTC2155CUP-14, observe proper analog/digital ground partitioning, place bypass capacitors as close as possible to AVDD/DVDD pins, and follow Analog Devices' differential input-balun network recommendations to realize the listed SNR/SFDR performance. Output data format and timing must match the chosen FPGA capture IP. This page synthesizes distributor pricing, drop-in alternatives drawn from the LTC2155 and pin-compatible Linear Technology/Analog Devices families, and practical design notes not consolidated in the manufacturer datasheet.
LTC2155IUP-12 - Dual 12-Bit 170Msps ADC, 1.8V, 64-QFN | Analog Devices
The Analog Devices LTC2155IUP-12 is a dual 12-bit, 170 Msps pipelined analog-to-digital converter (ADC) housed in a 64-pin QFN (9x9 mm) package. It operates from a single 1.8V supply, dissipates approximately 545 mW total power, and supports differential input signals with an easy-to-drive 1.5 Vp-p input range. The converter delivers 68.5 dB SNR and 90 dB SFDR, making it suitable for high-frequency wide-dynamic-range signal acquisition. An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that converts continuous-time analog voltages into discrete digital codes at a defined sample rate. Pipelined ADCs use a multi-stage architecture that enables high sampling rates while maintaining moderate resolution and low power. The LTC2155 belongs to the pipelined ADC sub-family of data converters, which sits within the broader category of mixed-signal ICs and signal-chain components. Key features of the LTC2155-12 family include DDR LVDS outputs for low-noise high-speed data transfer, an optional sample-and-hold front end, a clock duty-cycle stabilizer for jitter-tolerant sampling, and low-power Sleep and Nap modes. The 1.25 GHz full-power input bandwidth allows direct sampling of IF signals. A serial SPI port provides flexible configuration of output modes, gain, and channel selection. The 1.8V single-supply operation simplifies power-tree design in FPGA or ASIC co-located systems, while DDR LVDS outputs minimize pin count and reduce EMI by carrying data on differential edges. The pipelined core uses calibrated capacitor arrays and shared references between channels to keep channel-to-channel gain and offset matching tight. Typical applications include communications receivers (LTE/3G/4G base-station digitizers), radar and phased-array antenna IF sampling, broadband test-and-measurement instrumentation, medical imaging front-ends, and high-speed data acquisition systems. The wide input bandwidth also suits digital oscilloscope front-end channels. The pin-compatible 14-bit (LTC2155-14) and lower-speed family members provide upgrade and cost-down paths on the same PCB footprint. When designing with this device, route the differential analog inputs as length-matched 100-ohm transmission lines, keep the 1.8V analog supply isolated from noisy digital rails, and place the SPI configuration traces away from the LVDS output edges. The exposed pad must be soldered to a continuous ground plane for thermal dissipation and signal-return integrity. This page synthesizes distributor pricing, family upgrade/downgrade alternatives, and practical design notes not found in the manufacturer datasheet alone.
LTC2155IUP-14 - Dual 14-Bit 170Msps ADC, 64-QFN | Analog Devices
The Analog Devices LTC2155IUP-14 is a dual-channel, 14-bit, 170 Msps analog-to-digital converter (ADC) housed in a 64-pin QFN (9x9 mm, UP suffix) package with an exposed thermal pad. Designed for digitizing high-frequency, wide-dynamic-range signals, it operates from a single 1.8 V supply and requires differential analog inputs to achieve specified performance. What is a high-speed pipelined ADC? A pipelined analog-to-digital converter is a multi-stage architecture where each stage converts a portion of the input then passes a residue to the next stage; this topology trades conversion latency (typically a few clock cycles) for very high sampling rates while keeping per-stage comparator resolution manageable. The LTC2155IUP-14 sits within the ADC -> high-speed ADC -> pipelined ADC -> dual-channel ADC -> data converter -> signal chain IC hierarchy, and belongs to the precision data-converter sub-family targeting communications and instrumentation. Key specifications include: 14-bit resolution per channel, 170 Msps sample rate per channel (two simultaneous channels), 1.8 V single supply, SNR of 74.5 dBFS and SFDR of 90 dBFS typical at 70 MHz input (per the LTC2155-14 datasheet), LVDS digital outputs with configurable termination, and an external/internal reference option. The device integrates a PLL and supports both CMOS and DDR LVDS output modes. Per the manufacturer datasheet 21576514fb, full-power analog input bandwidth exceeds 600 MHz, allowing undersampling of IF signals. Architecturally, the LTC2155IUP-14 uses two interleaved 170 Msps pipelined cores, front-end track-and-hold amplifiers, an optional on-chip dither generator for improved SFDR at small input levels, and a digital output serializer that presents data on a DDR LVDS or CMOS bus. The internal reference simplifies board design; the external reference option enables gain calibration or shared reference across multiple ADCs in a system. Typical applications include digital oscilloscopes, wideband communications receivers (LTE/GSM base-station digital pre-distortion feedback paths), radar IF sampling, cable-modem head-ends, spectral analysis / signal intelligence, and medical imaging front-ends. The dual simultaneous-sampling channels permit I/Q or in-phase/quadrature direct-conversion signal chains without skew correction. Design consideration: drive each analog input differentially through a balun or transformer to avoid second-harmonic distortion; route the 1.8 V analog and digital supplies through separate ferrites to break ground loops between the noisy serializer and the sensitive input front-end. Always capture the full ADC calibration on power-up by issuing the desired calibration mode before normal data capture. This page synthesizes distributor pricing snapshots, drop-in same-package pin-compatible alternatives (LTC2155CUP-14 family variants and same-package Linear Technology speed/replacement options), and practical layout notes not aggregated on a single manufacturer page.
LTC2156CUP-12 - Dual 12-Bit 210Msps ADC, 64-QFN | Analog Devices
The Analog Devices LTC2156CUP-12 is a dual 12-bit, 210 Msps analog-to-digital converter designed for digitizing high-frequency, wide dynamic range signals in communications, radar, and test instrumentation. Each channel delivers 12-bit resolution at 210 Msps with a pipelined architecture and only five clock cycles of latency, packaged in a 64-lead QFN (UP package code, 9x9 mm) with an exposed pad for thermal dissipation. The part is part of the LTC2157-12 / LTC2156-12 / LTC2155-12 pin-compatible family, so 250 Msps and 170 Msps variants exist on the same footprint. A pipelined ADC is a successive-stage converter architecture that processes one sample per clock cycle after the initial pipeline fill, balancing high sampling rate with moderate die area. Pipelined ADCs sit within the broader hierarchy of analog-to-digital converter -> data converter -> signal chain IC -> mixed-signal semiconductor, and are the dominant topology for converter sampling rates above approximately 50 Msps where successive-approximation (SAR) and flash architectures become impractical. Key features of the LTC2156CUP-12 include typical DC linearity of ±0.26 LSB INL and ±0.16 LSB DNL, no missing codes over temperature, and a low transition noise of 0.54 LSBRMS. The differential analog inputs accept single-ended or differential drive, and the digital outputs are double-data-rate (DDR) LVDS for low-noise, high-speed interface to an FPGA or ASIC. The ENC+ and ENC- clock inputs can be driven differentially from a sine wave, PECL, LVDS, TTL, or CMOS source, simplifying clock distribution in multi-channel systems. Typical applications include multi-channel digital oscilloscopes, wideband radar digitizers, software-defined radio receivers, medical imaging front-ends (ultrasound beamformers), and communications test equipment such as vector signal analyzers. The dual-channel integration saves board area versus two discrete single-channel ADCs, and the pin-compatible family allows the same PCB to be populated with the 250 Msps LTC2157-12 or 170 Msps LTC2155-12 depending on system bandwidth needs. When designing with this part, follow the Analog Devices reference layout for the 64-QFN exposed-pad package: stitch the EP to a solid ground plane with multiple thermal vias, keep analog input traces length-matched and 100 ohm differential, and place the input network and reference decoupling capacitors as close to the pins as possible. The DDR LVDS interface requires careful length matching on the PCB to maintain the 210 Msps data eye margin.
LTC2156IUP-14 - Dual 14-Bit 210Msps ADC 64-QFN | Analog Devices
The Analog Devices LTC2156IUP-14 is a dual-channel, 14-bit, 210 Msps pipelined analog-to-digital converter (ADC) housed in a 64-pin (9 mm x 9 mm) QFN package, designed for the simultaneous sampling of high-frequency, wide dynamic-range signals. It draws 650 mW from a single 1.8 V supply and delivers 70 dB SNR with 90 dB SFDR, with DDR LVDS outputs and a serial SPI port for configuration. The -14 industrial temperature grade operates from -40 C to +85 C. A pipelined ADC is a multi-stage converter architecture that digitizes an analog input through a cascade of low-resolution flash sub-converter stages combined with inter-stage residue amplification and digital error correction. Pipelined ADCs occupy the middle ground between low-power successive-approximation (SAR) converters and very-high-speed flash ADCs, delivering hundreds of megasamples per second at moderate resolution. In a system hierarchy, the LTC2156IUP-14 belongs to the broader category of data converters -> analog-to-digital converters (ADCs) -> high-speed ADCs -> pipelined ADCs, which is one of the principal building blocks of modern signal acquisition and digital signal processing (DSP) systems. Key features include dual simultaneous-sampling channels, an easy-to-drive 1.5 V peak-to-peak differential input range, 1.25 GHz full-power sample-and-hold bandwidth, an optional on-chip clock duty-cycle stabilizer, and low-power Sleep and Nap modes for power-constrained systems. The serial SPI port enables register-level configuration of output formats, gain, and calibration, while DDR LVDS outputs ease the board-level routing of high-speed digital data into an FPGA or ASIC. Typical applications include communications basestations, radar digitizers, medical imaging front-ends, and high-end test and measurement instrumentation. The wide SFDR and fast sampling rate allow direct digitization of IF signals in software-defined radio (SDR), while the dual channels support MIMO or I/Q signal chains. A 1.5 Vp-p input range simplifies the front-end driver design relative to competitors that require 2 Vp-p swings. When designing with this device, place bypass capacitors as close as possible to the supply pins and route the differential analog inputs as a tightly-coupled pair to preserve common-mode rejection at the rated SFDR. The clock trace must be short and well-terminated to meet the 210 Msps conversion rate without violating setup-and-hold timing into the receiver.
LTC2157CUP-12 - Dual 12-bit 250Msps ADC, 64-QFN | Analog Devices
The Analog Devices LTC2157CUP-12 is a dual-channel, 12-bit, 250 Msps pipelined analog-to-digital converter housed in a 64-lead 9mm x 9mm QFN package. It delivers 68.5 dB SNR and 90 dB SFDR, draws 628 mW total power from a single 1.8 V supply, and provides DDR LVDS digital outputs for high-speed downstream capture into FPGAs or ASICs. The device integrates two matched sample-and-hold front ends, an on-chip clock duty-cycle stabilizer, and a serial SPI port for per-channel configuration. What is a pipelined ADC? A pipelined analog-to-digital converter is a high-speed successive-approximation architecture that processes each input sample through a cascade of low-resolution stages, each stage converting a residual and passing the amplified remainder to the next. This sub-ranging approach trades a small fixed conversion latency (typically a few clock cycles) for very high sampling rates - 100 Msps to over 1 Gsps - making pipelined ADCs the workhorse of communications, radar, medical imaging, and digital oscilloscope front ends. Key features of the LTC2157CUP-12 include an easy-to-drive 1.5 Vp-p input range that simplifies front-end driver selection, 1.25 GHz full-power input bandwidth, optional clock duty-cycle stabilizer for jitter-sensitive applications, and low-power Sleep and Nap modes for power-cycled receiver chains. The dual-channel integration halves board area versus two discrete ADCs, and the 64-pin QFN exposes two matched analog inputs that share a common reference and clock. Typical applications include multi-carrier wireless base-station receivers, radar signal acquisition, medical imaging front ends, cable-headend QAM demodulators, and high-speed digital oscilloscope input channels. Designers select this part when 12-bit resolution is sufficient and 250 Msps per channel is required in a tight footprint. When designing with the LTC2157CUP-12, ensure the LVDS output traces are length-matched within 25 mil to meet DDR timing and that the exposed pad is soldered with at least 4 thermal vias for the rated power dissipation. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
LTC2157CUP-14 - Dual 14-Bit 250Msps ADC | Analog Devices
The Analog Devices LTC2157CUP-14 (also marketed as LTC2157CUP-14#PBF) is a dual-channel, 14-bit, 250 Msps pipelined analog-to-digital converter (ADC) housed in a 64-pin QFN (9 mm x 9 mm) package. The converter is powered from a single 1.8 V supply, supports differential analog inputs, and provides DDR LVDS digital outputs. According to the manufacturer datasheet 21576514fb, the device achieves 70 dB SNR, 90 dB SFDR, and consumes 650 mW total power. An ADC (analog-to-digital converter) is a semiconductor device that converts continuous-time analog signals into discrete digital codes. The LTC2157-14 belongs to the pipelined ADC sub-family, which uses multiple cascaded low-resolution stages to achieve high sample rates while maintaining 14-bit resolution. Within the broader taxonomy, this part is a data converter -> ADC -> high-speed pipelined ADC -> dual-channel simultaneous-sampling ADC. Pipelined ADCs are widely used in communications infrastructure, defense electronics, and test and measurement equipment where both speed and resolution matter. Key features of the LTC2157CUP-14 include a 1.5 Vp-p easy-to-drive input range, 1.25 GHz full-power sample-and-hold bandwidth, an optional clock duty cycle stabilizer, low-power sleep and nap modes, and a serial SPI port for per-channel configuration. The dual channels support either external or internal voltage reference and offer simultaneous sampling for I/Q or diversity receiver architectures. Pin-compatible 12-bit versions are available (LTC2157-12 family), allowing design scalability across resolution requirements. The architecture is a 14-stage pipelined ADC with proprietary internal calibration, supporting 250 Msps per channel and offering 1:1 S/H-to-ADC ratio. The LVDS DDR outputs ease FPGA/ASIC capture and reduce pin count on the board. The internal reference simplifies BOM, while the external reference option enables system-wide gain calibration in high-linearity applications. Typical applications include software-defined radio (SDR) receivers, MIMO LTE/WiMAX transceivers, multi-channel data acquisition systems, medical imaging front-ends, and radar/EW signal processing. The dual simultaneous-sampling channels also suit I/Q demodulation and direct-conversion receiver chains. When designing with this part, place the analog input traces as a 50 ohm differential pair with controlled 100 ohm differential impedance, and keep LVDS outputs length-matched to within 50 mil to preserve timing margin. A solid ground plane beneath the QFN exposed pad is required for thermal dissipation at full sample rate. This page synthesizes Analog Devices distributor pricing as of 2026-10-13, drop-in same-family alternatives from the LTC215x-14 series, and practical PCB/layout design notes not duplicated in the manufacturer datasheet.
LTC2157IUP-12 - Dual 12-Bit 250Msps ADC | Analog Devices
The Analog Devices LTC2157IUP-12#PBF is a dual-channel, 12-bit, 250 Msps analog-to-digital converter (ADC) housed in a 64-lead QFN (9 mm × 9 mm) package with exposed pad. The part accepts differential analog inputs with an easy-to-drive 1.5 Vp-p input range, samples both channels simultaneously, and outputs data on DDR LVDS rails from a single 1.8 V supply. The 'IUP' suffix designates the industrial temperature grade of -40 °C to +85 °C, while the 'CUP' commercial variant operates over 0 °C to +70 °C. An ADC (analog-to-digital converter) is a data-conversion IC that transforms continuous analog signals into discrete digital codes for downstream processing by an FPGA, ASIC, or DSP. Within the signal chain it sits between the analog front end (amplifier/filter) and the digital back end, and high-speed pipeline ADCs like the LTC2157 family target wideband IF sampling, communications receivers, and test instrumentation. In the broader taxonomy: ADC -> data converter -> mixed-signal IC -> semiconductor. Key headline specifications include 250 Msps per channel (500 Msps interleaved effective throughput), 70 dB SNR and 90 dB SFDR typical, an input full-power bandwidth of 1.25 GHz, and low power consumption of approximately 650 mW total for the dual-channel device. The part integrates a sample-and-hold, an optional clock duty-cycle stabilizer, low-power sleep and nap modes, and a serial SPI port for mode configuration, eliminating the need for external support logic. Architecturally, the LTC2157-12 uses a multi-stage pipelined converter core with digital error correction. The DDR LVDS interface halves the output pin count and lets the FPGA capture data on both clock edges, simplifying board routing at 250 Msps line rates. The pin-compatible family includes the 14-bit LTC2157-14 and the lower-speed LTC2156-12 (210 Msps) and LTC2155-12 (170 Msps), enabling system scaling without PCB rework. Typical applications include multi-channel communications receivers, MIMO radar digitizers, software-defined radio (SDR) front ends, medical imaging front ends, and high-speed data acquisition systems. The wide input bandwidth supports undersampling of IF signals centered well above Nyquist, while the low power simplifies thermal design in dense multi-channel arrays. When designing with this part, route the 1.8 V analog and digital supplies as separate islands joined at a single ferrite bead, place the 0.1 µF + 10 µF decoupling network within 2 mm of each supply pin, and provide a low-jitter differential clock (PECL/LVDS) to achieve the published SNR. Use the exposed pad as the primary thermal path, soldering it to a continuous ground plane with multiple thermal vias. This page synthesizes authorized distributor pricing, datasheet-cited specifications, and drop-in pin-compatible alternatives from the same LTC215x family - engineering information that helps select the right resolution/speed combination for your signal chain.
LTC2158CUP-14 - Dual 14-Bit 310Msps ADC | Analog Devices
The Analog Devices LTC2158CUP-14 is a 2-channel simultaneous sampling 310Msps 14-bit pipelined analog-to-digital converter housed in a 64-lead QFN (9x9 mm) package. It is engineered for digitizing high-frequency, wide dynamic-range signals, delivering 68.8 dB SNR and 88 dB spurious-free dynamic range (SFDR) at the full 310 Msps conversion rate. The 1.25 GHz analog input bandwidth enables IF undersampling of high-frequency carriers while preserving AC linearity. A pipelined ADC is a multi-step converter architecture that processes one conversion stage per clock cycle, allowing very high sample rates (hundreds of Msps to Gsps) while keeping per-stage comparator requirements modest. Within the broader signal-chain hierarchy, the LTC2158CUP-14 sits as an analog-to-digital converter -> data converter -> mixed-signal IC -> semiconductor. Its dual simultaneous-sampling channels make it a member of the high-speed pipeline-ADC family targeted at communications infrastructure, radar, and instrumentation. Key features include dual simultaneous-sampling 14-bit 310 Msps conversion per channel, 68.8 dB SNR and 88 dB SFDR for wide dynamic-range capture, 1.25 GHz analog input bandwidth for IF sampling, 355 mA supply current from a 1.7 V to 1.9 V analog/digital supply, and an exposed-pad QFN-64 (9x9) package for low thermal resistance. The integrated input common-mode bias simplifies transformer or op-amp driver interfaces. The device uses a multi-stage differential pipeline core with on-chip reference and sample-and-hold, supporting CMOS or DDR LVDS output formats for flexible FPGA/ASIC capture. LVDS outputs simplify board layout and reduce digital switching noise coupling into the analog front end. Typical applications include communications receivers, cellular base-station digitizers, radar and phased-array signal processing, test and measurement instrumentation, and high-performance imaging. Dual simultaneous channels allow I/Q capture or diversity reception from a single converter IC. When designing with the LTC2158CUP-14, decouple each analog and digital supply pin individually, route the LVDS outputs with 100 ohm differential impedance, and provide a low-jitter clock to CLK+ and CLK- to preserve SNR at full rate. The exposed pad must be soldered to a continuous ground plane for thermal dissipation and electrical reference. This page synthesizes verified distributor pricing, drop-in QFN-64 same-family alternatives, and practical PCB/decoupling design notes not found in the manufacturer datasheet alone.
LTC2159CUK - 16-Bit 20Msps Low Power ADC | Analog Devices
The Analog Devices LTC2159CUK is a 16-bit, 20 Msps low-power pipelined analog-to-digital converter (ADC) housed in a 48-lead QFN (7 mm x 7 mm) package. It is engineered for digitizing high-frequency, wide-dynamic-range signals and offers AC performance of 77 dB SNR and 90 dB spurious-free dynamic range (SFDR), making it suitable for demanding communications and instrumentation front ends. A pipelined ADC is a high-speed sampling converter that uses multiple cascaded low-resolution flash stages and a digital correction engine to deliver high bit resolution at sample rates from a few MHz to several hundred MHz. Within the broader converter taxonomy, the LTC2159CUK belongs to the successive-approximation-adjacent high-speed family that sits between precision SAR ADCs (>1 Msps, low noise) and ultra-high-speed flash ADCs (>1 Gsps, low resolution). Pipeline ADCs trade latency for throughput and are the de-facto standard for wideband IF sampling, software-defined radio, and digital oscilloscope front ends. Key differentiating specifications include 77 dB SNR at baseband, 90 dB SFDR, single 1.8 V analog supply operation, CMOS or DDR LVDS digital outputs with a separate 1.2 V to 1.8 V output supply, and very low power consumption (per the datasheet, total power is approximately one third of competing 16-bit/20 Msps parts). The integrated input network simplifies front-end design, and an internal clock duty-cycle stabilizer preserves AC performance even with poor clock sources. Architecturally, the part combines a fully differential input buffer, a multi-stage switched-capacitor pipeline, and an LVDS/CMOS serializer, all clocked by a single-ended or differential encoding input. Digital-output formatting is selectable: full-rate CMOS, double-data-rate CMOS, or double-data-rate LVDS to ease interfacing with FPGAs and ASICs of varying I/O standards. Typical applications include high-end communications receivers (LTE/3G base-station digitizers), radar IF sampling, cable-infrastructure head-ends, medical imaging (ultrasound I/Q demodulation), and high-density portable test instruments. For each of these, the combination of 16-bit resolution, 20 Msps, low power, and small 7 mm x 7 mm QFN footprint reduces board area and thermal budget. Design consideration: when digitizing signals above the first Nyquist, ensure the front-end anti-alias filter has stop-band attenuation beyond 77 dB over the relevant image band, and provide a low-jitter clock to preserve SNR. At higher input frequencies, SNR degrades predictably, so select the input drive network to match the recommended source impedance. This page synthesizes distributor pricing, packaged variants, and cross-reference alternatives that complement what is shown on the manufacturer product page.
LTC2161CUK - 16-Bit 40Msps Low Power ADC | Analog Devices
The Analog Devices LTC2161CUK is a 16-bit, 40 Msps low-power pipelined analog-to-digital converter (ADC) housed in a 48-pin QFN (7x7 mm) package with exposed pad. Designed for digitizing high-frequency, wide-dynamic-range signals, it delivers 77 dB SNR and 90 dB spurious-free dynamic range (SFDR), with ultralow 0.07 ps RMS aperture jitter that enables excellent undersampling of IF frequencies. The commercial temperature grade is supported by the C-suffix variant. A digitized output price starting at $40.69 per 1ku on the manufacturer's product page reflects the part's positioning in performance-tier precision converters. An ADC (analog-to-digital converter) is a semiconductor device that converts continuous analog voltage signals into discrete digital codes, forming the essential bridge between the analog sensor/frontend world and the digital signal-processing/back-end world. Within the converter hierarchy, the LTC2161 belongs to the pipelined-architecture family, which subdivides the conversion into multiple low-resolution stages to balance speed, resolution, and power efficiency. Pipelined ADCs > successive-approximation ADCs in speed > analog-to-digital converters > data converters > signal-chain ICs > semiconductors. The 16-bit resolution with 40 Msps sampling makes this part appropriate for instrumentation, communications, and industrial imaging where both dynamic range and acquisition speed matter. Key features of the LTC2161 include pin-selectable single-ended or differential analog inputs, programmable digital output formats including CMOS and LVDS, internal bypass reference, and a low-power architecture that is significantly reduced compared with earlier-generation 16-bit pipelines. The differential analog input architecture provides excellent common-mode noise rejection, while the integrated duty-cycle stabilizer (DCS) compensates for clock duty-cycle distortion, easing clock-tree constraints in the host FPGA or ASIC. Technically, the LTC2161 utilizes a multi-stage pipelined architecture with output error correction in each stage, followed by a digital post-processing block. This approach allows the device to deliver a true 16-bit code with maintained linearity across the full Nyquist band, supported by the 0.07 ps RMS jitter figure that keeps SNR high even on aggressive input slew rates. The 48-QFN package features an exposed thermal pad, which must be soldered to the PCB ground plane to provide the low-impedance return paths necessary for the LVDS/CMOS outputs and to dissipate converter self-heating. Typical applications include high-end communications receivers, IF-sampling software-defined radios, medical imaging (ultrasound beamformers, MRI digitizers), instrumentation and oscilloscopes, multi-channel data acquisition systems, and spectrum analyzer front-ends. The wide dynamic range supports direct digitization of RF intermediate frequencies without a preceding mixer stage in many block diagrams. Design tip: provide an ultra-low-jitter sampling clock to the LTC2161's CLK input, since jitter rather than quantisation often dominates SNR degradation at high input frequencies. When using LVDS outputs, maintain 100-ohm differential transmission-line terminations and match trace lengths to keep channel-to-channel skew within the FPGA capture window. This page synthesizes distributor pricing, drop-in alternative candidates, and practical design notes that are not duplicated in the manufacturer datasheet alone, supporting faster component selection and sourcing decisions.
LTC2162IUK - 16-Bit 65Msps Low Power ADC | Analog Devices
The Analog Devices LTC2162IUK is a 16-bit, 65 Msps pipelined analog-to-digital converter (ADC) optimized for high-frequency, wide-dynamic-range signal acquisition, supplied in a 52-lead 7x7 mm QFN exposed-pad (UK) package. It delivers 77 dB SNR and 90 dB spurious-free dynamic range (SFDR), with ultralow aperture jitter of 0.07 ps RMS that permits reliable undersampling of IF frequencies in communications systems. What is a pipelined ADC: A pipelined analog-to-digital converter is a multi-stage sampling converter that processes analog input through a cascade of low-resolution flash stages and a digital error-correction back end. Pipelined ADCs sit within the hierarchy of Nyquist ADCs and offer the best trade-off between sample rate, resolution, and power consumption, making them the workhorse of communications infrastructure, test instrumentation, and software-defined radio. The converter integrates a single differential input channel, an internal reference, and configurable digital outputs ranging from CMOS/LVDS parallel to serial SPI/LVDS, allowing direct interface to FPGAs, DSPs, and ASICs. Differential analog inputs (1 Vp-p or 2 Vp-p) feed an internal sample-and-hold, simplifying front-end design. Maximum power dissipation is approximately 140 mW at 65 Msps with CMOS output, suiting thermally constrained dense boards. The integrated bandgap reference, clock duty-cycle stabilizer, and programmable digital gain/offset calibration remove the need for external circuitry in many applications. Internal reference can also be overdriven for best gain-drift performance in instrumentation. Typical applications include communications receivers, software-defined radio (SDR), basestation IF sampling, portable instrumentation, ultrasound imaging front ends, and multichannel data-acquisition systems. The wide input bandwidth (>300 MHz differential) also supports direct IF sampling of cellular and cable-infrastructure signals. When designing with this device, ensure the analog input common-mode bias is well-bypassed and that the exposed pad is soldered to a low-impedance ground plane for thermal relief. The internal duty-cycle stabilizer removes the need for an external clock jitter-cleaner at sample rates up to 65 Msps, but upstream PLL jitter still degrades SNR. This page synthesizes authorized distributor pricing, pin-to-pin drop-in alternatives within the QFN-52 footprint, and practical PCB-layout guidance not consolidated in the manufacturer datasheet, helping engineers choose between the LTC2162, LTC2161, and LTC2160 speed grades with full design context.
LTC2163IUK - 16-Bit 80Msps Low Power ADC | Analog Devices
The Analog Devices LTC2163IUK is a 16-bit, 80 Msps low-power pipelined analog-to-digital converter (ADC) housed in a 48-pin QFN (7x7 mm) package with exposed pad. The converter is designed for digitizing high-frequency, wide-dynamic-range signals and delivers 76.8 dB SNR and 90 dB spurious-free dynamic range (SFDR), with an ultralow aperture jitter of 0.07 ps RMS that allows clean undersampling of IF frequencies. What is a pipelined ADC? A pipelined analog-to-digital converter is a high-speed sampling architecture that breaks the conversion process into multiple low-resolution stages. Each stage samples and converts a coarse portion of the input, then passes a residue to the next stage. Pipelined ADCs are the dominant architecture for 8-bit to 16-bit sampling at 20 Msps to 500 Msps, sitting within the broader hierarchy of ADC -> data converter -> mixed-signal IC -> semiconductor. They are favored when both speed and resolution matter, as in communications, instrumentation, and imaging. Key features of the LTC2163IUK include selectable CMOS, LVDS, or DDR LVDS parallel interfaces, a 1.8 V analog supply, an optional low-noise bypass mode, and 1.4 W typical power dissipation at 80 Msps. Differential input drive with an internal reference simplifies front-end design, while the exposed pad provides a low thermal-resistance path (around 28 C/W theta_JA) for reliable operation at full sampling rate. The device operates from a single 1.8 V supply, with separate analog and digital supply pins to minimize coupling noise. Its pipelined core stages are calibrated at power-up using an internal state-machine routine. Digital output data is presented on 16 parallel lanes, configurable for CMOS single-data-rate or LVDS double-data-rate modes. Typical SNR of 76.8 dB and SFDR of 90 dB at 70 MHz input make it well-suited for software-defined radio and cellular base-station digitizers. Typical applications include software-defined radio, cellular base-station receivers, IF sampling for communications systems, medical imaging front ends, and industrial ultrasound signal chains. The wide input bandwidth and low jitter support undersampling architectures that reduce system BOM. When designing with the LTC2163IUK, ensure the analog input common-mode voltage is set correctly (typically 0.9 V internal) and use a low-jitter clock driver. Provide a solid ground plane under the exposed pad, stitching vias around the perimeter, and decouple each supply pin with a 0.1 uF ceramic plus a 10 uF bulk capacitor within 2 mm of the pin. This page synthesizes distributor pricing, drop-in same-package alternatives, application companion MPNs, and PCB layout guidance not aggregated on the manufacturer datasheet or typical distributor pages.
LTC2164CUK - 16-Bit 105Msps Low Power ADC | Analog Devices
The Analog Devices LTC2164CUK is a 16-bit, 105 Msps low-power pipelined analog-to-digital converter (ADC) housed in a 48-pin QFN (7x7) package with exposed pad. It delivers 76.8 dB SNR and 90 dB spurious-free dynamic range (SFDR) at the full 105 Msps sample rate, while consuming roughly 120 mW from a single 1.8 V supply. An ultralow 0.07 psRMS aperture jitter allows reliable undersampling of IF frequencies, making the part well suited for communications and radar-class signal chains. An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that samples a continuous analog waveform and produces a discrete multi-bit digital representation. Pipelined ADCs, the family to which the LTC2164CUK belongs, use a multi-stage sub-ADC/MDAC/flash architecture to achieve 14-16 bit resolution at tens to hundreds of mega-samples per second while keeping per-stage hardware costs manageable. Within the broader taxonomy, the LTC2164CUK sits at: ADC -> pipelined ADC -> data converter -> mixed-signal IC -> semiconductor. Pipelined parts are the dominant choice for communications infrastructure, defense electronics and high-end instrumentation where 16-bit dynamic range at IF frequencies is mandatory. Key features of the LTC2164CUK include a single 1.8 V analog supply (with separate digital output supply rail for flexible interfacing), selectable CMOS, DDR CMOS or LVDS output modes, a serial SPI port for mode configuration, integrated shutdown and nap power-save modes, and AC performance that targets demanding communications front-end applications. The part accepts single-ended or differential analog inputs and provides an integrated input common-mode bias network, reducing the external component count on the front-end anti-alias filter. The LTC2164CUK uses a switched-capacitor pipelined core calibrated at the Analog Devices factory. Internal error-correction logic and digital post-processing yield consistent 76.8 dB SNR and 90 dB SFDR across the IF band of interest. Designers typically pair it with a low-jitter ADC clock buffer (e.g. AD9516 or HMC7044) and a bandpass anti-alias filter. Differential transformer coupling (e.g. ADT1-1WT or Mini-Circuits ADT2-1T) is the standard input configuration to preserve second-order distortion performance. Typical applications for the LTC2164CUK include wireless base-station receivers, LTE/UMTS and CDMA digitizing IF stages, radar and electronic-warfare intermediate-frequency sampling, broadband software-defined radio (SDR), cable-headend downstream digitizers, and high-end medical imaging front ends. The combination of 16-bit resolution and 105 Msps throughput also makes it useful in scientific test instrumentation and ultrasonic nondestructive testing. A key design consideration with the LTC2164CUK is clock jitter. Although the part's 0.07 psRMS aperture jitter is exceptionally low, total system SNR is dominated by the analog input frequency multiplied by external clock jitter. Designers should budget at least 0.5 ps of clock-source jitter for IF inputs above 70 MHz, and use a dedicated clock distribution buffer or PLL to keep the sampling edge clean. The exposed pad of the QFN-48 must be soldered to a continuous low-impedance ground plane for thermal and electrical performance. This page synthesizes distributor stock and pricing, drop-in pin-compatible alternatives, and practical PCB layout notes that supplement the official Analog Devices datasheet family.
LTC2164IUK - 16-Bit 105Msps Low Power ADC | Analog Devices
The Analog Devices LTC2164IUK is a 16-bit, 105 Msps low-power pipelined analog-to-digital converter (ADC) housed in a 48-pin QFN (7x7 mm) package. It integrates one differential/CMOS-compatible input channel and delivers 76.8 dB SNR and 90 dB spurious-free dynamic range (SFDR), making it well suited for demanding wide-bandwidth communications, instrumentation, and IF-sampling applications. Ultralow 0.07 ps RMS aperture jitter enables accurate undersampling of intermediate-frequency (IF) signals far above Nyquist. What is a pipelined ADC? A pipelined ADC is a multi-stage converter architecture that resolves a high-frequency analog input by passing it through a cascade of low-resolution flash stages interleaved with sample-and-hold amplifiers and digital error correction. Each stage performs a coarse conversion, computes a residue, and feeds the residue to the next stage. Within the broader taxonomy, the LTC2164 sits in the chain: ADC -> data converter -> mixed-signal IC -> semiconductor. Pipelined ADCs dominate the >10 Msps, >12-bit converter market because they deliver the best trade-off among speed, resolution, and power consumption. Key features of the LTC2164IUK include 105 Msps sampling rate, 16-bit resolution, 76.8 dB SNR, 90 dB SFDR, 0.07 ps RMS jitter, an integrated high-bandwidth differential sample-and-hold front end, selectable CMOS/LVDS output modes, and an internal reference (with optional external reference override). The part operates from a single 1.8 V analog supply plus a separate digital output supply (1.8 V CMOS mode, or 2.5 V LVDS mode), and consumes only 150 mW typical at full speed with CMOS outputs. The 48-QFN (7x7) package is thermally efficient and exposes a die-attach pad that must be soldered to a low-impedance ground pour. Internal register programmability is accessed via a 3-wire SPI-compatible serial interface. The architecture supports both single-ended and differential analog inputs, which simplifies front-end design across multiple baseband and IF topologies. Together these characteristics make the LTC2164 a flexible ADC for software-defined radio, LTE/4G base stations, medical imaging front ends, and high-speed data acquisition. Typical applications include communications basestations (LTE, WiMAX, GSM/EDGE), medical imaging ultrasound front ends, high-speed test and measurement instrumentation (digitizers, oscilloscopes, spectrum analyzers), IF undersampling in software-defined radio, and radar/LIDAR signal chains. When designing with the LTC2164IUK, pay close attention to analog input common-mode bias, clock duty-cycle stability, and the LVDS/CMOS output supply choice. Decoupling must include dedicated low-ESL/ESR capacitors placed within 2 mm of each supply pin. The exposed pad (EP) is the primary thermal path and must be soldered to a continuous ground plane for rated performance. This page synthesizes distributor pricing, verified drop-in alternatives, and practical design guidance not found on a single distributor listing or in the bare datasheet, providing engineers with an actionable evaluation summary.
LTC2165CUK - 16-Bit 125Msps Low Power ADC | 48-QFN
The Analog Devices LTC2165CUK is a 16-bit, 125 Msps low-power pipelined analog-to-digital converter (ADC) housed in a 48-pin QFN (7x7) package with exposed pad. It features a single differential or single-ended analog input channel and CMOS-compatible digital outputs, making it suitable for digitizing high-frequency, wide-dynamic-range signals in communications and instrumentation systems. The converter achieves 76.8 dB SNR and 90 dB spurious-free dynamic range (SFDR), with ultralow 0.07 ps RMS aperture jitter that allows accurate undersampling of IF frequencies. The C-grade commercial temperature variant operates from 0 °C to +70 °C, while the I-grade LTC2165IUK covers the industrial range from -40 °C to +85 °C. An ADC is a data converter that transforms continuous-amplitude, continuous-time analog signals into discrete-amplitude, discrete-time digital codes. The pipelined ADC architecture used by the LTC2165CUK cascades multiple low-resolution flash stages to achieve high resolution at high sample rates while keeping per-stage bandwidth moderate. Within the broader converter taxonomy, the LTC2165CUK belongs to SAR/pipelined ADCs -> data converters -> signal chain ICs -> mixed-signal semiconductors. Pipelined ADCs dominate the 16-bit, 50-200 Msps tier because they balance speed, resolution, and power more efficiently than successive-approximation (SAR) or flash architectures. Key specifications include 16-bit resolution, 125 Msps maximum sample rate, single 1.8 V analog supply (with a separate 1.8 V to 3.3 V digital supply for output logic levels), approximately 158 mW total power dissipation, 76.8 dB SNR at 70 MHz input, 90 dB SFDR, and 0.07 ps RMS jitter. Differential nonlinearity (DNL) is typically ±0.4 LSB and integral nonlinearity (INL) is typically ±1.0 LSB. The device accepts single-ended or differential inputs and includes an internal reference, an optional external reference input, and a clock-duty-cycle stabilizer. Typical applications include cellular base-station receiver IF digitizers, cable-headend downstream QAM demodulators, test and measurement instrumentation, software-defined radio (SDR) front-ends, radar and lidar signal processing, medical imaging receivers, and broadband communications. The wide analog input bandwidth and ultralow jitter also make it ideal for direct-IF sampling in digital receivers. When designing with this part, follow the standard layout practice of stitching the exposed pad to a solid ground plane for thermal dissipation and ground reference, place the input network as close to the analog input pins as possible, and treat the analog and digital supplies as independent rails with separate decoupling. Note that the C-suffix denotes commercial temperature range; the I-suffix LTC2165IUK is required for industrial-grade environments. This page synthesizes distributor pricing, drop-in alternative cross-references, and practical design notes that are not found in the manufacturer datasheet alone, providing an engineer-ready reference for the LTC2165CUK.
LTC2165IUK - 16-Bit 125Msps Low Power ADC | Analog Devices
The Analog Devices LTC2165IUK is a 16-bit, 125 Msps low-power pipelined analog-to-digital converter (ADC) housed in a 48-pin QFN (7x7 mm) UK package. It supports one differential or single-ended analog input and delivers 76.8 dB SNR with 90 dB spurious-free dynamic range, making it well-suited for digitizing high-frequency wideband signals in communications and instrumentation applications. An ADC, or analog-to-digital converter, is a semiconductor device that samples continuous analog voltage signals and converts them into discrete digital codes at a specified sampling rate. Pipelined ADCs like the LTC2165 employ a multi-stage sub-ADC architecture that interleaves conversions to achieve high sample rates while maintaining low power and small die area. They sit within the broader hierarchy of data converters, which includes successive-approximation (SAR), delta-sigma, and flash ADCs, and are the workhorse of high-speed signal acquisition systems. Key features of the LTC2165IUK include ultralow 0.07 ps RMS aperture jitter for accurate undersampling of IF frequencies, selectable LVDS/CMOS output modes for flexible board interfacing, an internal 2.5 V reference, and a maximum power dissipation of 314 mW at full 125 Msps operation. The pipelined architecture introduces a fixed conversion latency but supports continuous streaming with no cycle loss in either the CMOS or LVDS mode. The LTC2165IUK shares an identical pinout with the lower-speed LTC2164 (105 Msps) and LTC2163 (80 Msps) variants, allowing a single PCB layout to serve multiple performance targets. Digital outputs can be configured as full-rate CMOS, multiplexed CMOS for low-pin-count interfaces, or LVDS for high-noise-immunity backplanes. An internal reference and flexible input common-mode range simplify the analog front-end design. Typical applications include multiband, multimode cellular base-station receivers, software-defined radio (SDR) front ends, low-power handheld test instruments, medical imaging receivers, and spectrum analysis systems. The 125 Msps sampling rate combined with 16-bit resolution allows direct digitization of signals at IF frequencies such as 70 MHz or 140 MHz, simplifying receiver signal chains. Designers should pay attention to analog input network design: a wideband transformer or differential amplifier driver is recommended to preserve SFDR at high input frequencies, and a low-jitter sampling clock must be provided through a CMOS or LVPECL source to maintain the rated SNR. Decoupling must include a low-inductance 1 uF and 0.1 uF pair near the supply pins. This page synthesizes distributor pricing, pin-compatible speed-grade alternatives within the LTC2163/2164/2165 family, and practical design notes not found concisely in the manufacturer datasheet.
LTC2170CUKG-12 - 12-Bit Quad 25Msps ADC | Analog Devices
The Analog Devices LTC2170CUKG-12 is a 12-bit, 4-channel simultaneous-sampling pipelined analog-to-digital converter (ADC) supporting up to 25 Msps per channel, packaged in a 52-pin QFN (7 mm x 8 mm). It is pin-compatible with the 14-bit LTC2170-14 family members, enabling a single PCB design to be populated with 12-bit or 14-bit resolution parts without layout changes. The part operates from a single 1.8 V supply, dissipating approximately 160 mW total (40 mW per channel), making it one of the lowest-power quad 12-bit ADCs in its speed class. What is a pipelined ADC? A pipelined analog-to-digital converter is a multi-stage converter architecture that processes one sample per clock cycle after an initial pipeline-fill latency, providing an excellent trade-off between speed, resolution, and power consumption. Pipelined ADCs sit in the hierarchy of ADC architectures between flash converters (highest speed, lowest resolution) and successive-approximation-register (SAR) converters (lowest speed, highest accuracy at low sample rates), and are widely used in communications, imaging, and multi-channel data acquisition where tens of Msps are required with moderate resolution. Key features of the LTC2170CUKG-12 include 4 simultaneous-sampling differential or single-ended inputs, 800 MHz full-power analog input bandwidth, selectable input ranges of 1 Vp-p to 2 Vp-p, a sample-and-hold on each channel, 90 dB spurious-free dynamic range (SFDR), serial LVDS digital outputs (one or two bits per channel), and an SPI port for configuration. Shutdown and Nap modes reduce power during idle periods for battery-sensitive applications. The device uses a 1.8 V analog supply plus an optional 1.8 V digital supply, with an internal PLL generating all required clock phases. Its 52-pin QFN package provides a compact footprint and an exposed pad for thermal management, supporting reliable operation across the -40 °C to +85 °C commercial temperature range. Typical applications include multi-channel digital oscilloscopes, phased-array ultrasound receivers, MIMO wireless infrastructure baseband digitizers, radar and electronic-warfare front ends, medical imaging receivers, and high-speed data acquisition cards for industrial test equipment. The 4-channel simultaneous sampling is particularly valuable when channel-to-channel phase relationships must be preserved. When designing with this part, ensure the analog input is AC- or DC-coupled through a wideband low-distortion driver, place 0.1 µF bypass capacitors as close as possible to every supply pin, and provide a 100 Ω differential termination at each LVDS output pair. Verify the encoder/decoder mode and serial LVDS data-rate configuration through the SPI port during board bring-up. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, giving engineers a single reference for sourcing and qualifying the LTC2170CUKG-12.
LTC2170CUKG-14 - 14-Bit, 25Msps Low Power Quad ADC | ADI
The Analog Devices LTC2170CUKG-14 is a 14-bit, 25Msps low-power quad analog-to-digital converter (ADC) housed in a 52-pin QFN (7 mm x 8 mm) package with exposed thermal pad. It integrates four simultaneously-sampling pipelined ADC channels with 90 dB SFDR, sample-and-hold front-ends, and selectable serial LVDS outputs (one or two bits per channel), making it ideal for multi-channel baseband digitisation where PCB real estate is constrained. A pipelined ADC is a high-speed converter architecture that resolves an analog input through a cascade of low-resolution stages with inter-stage digital error correction. Quad-channel ADCs like the LTC2170-14 family fall under the broader data-converter hierarchy: ADC -> data converter -> mixed-signal IC -> semiconductor. By sharing one clock, reference and digital interface across four channels, designers replace four discrete ADC ICs, reducing BOM count, board area, and channel-to-channel skew compared to discrete multi-ADC solutions. Key specifications include 14-bit resolution at 25 Msps per channel, 90 dB spurious-free dynamic range (SFDR), single 1.8 V supply operation, and total power dissipation of 162 mW (about 41 mW per channel). Each channel has 800 MHz full-power analogue bandwidth, selectable 1 Vp-p or 2 Vp-p input ranges, an integrated sample-and-hold, plus shutdown and nap modes controlled through the serial SPI configuration port. The 52-pin QFN package offers low thermal resistance via the bottom exposed pad for heat transfer into the PCB copper plane. Typical applications include portable ultrasound imaging, multi-channel communication receivers, low-power instrumentation, and industrial imaging arrays. The pin-compatible 12-bit and 14-bit family members (LTC2170-12 / LTC2170-14) share the same footprint, allowing system designers to upgrade resolution or sample rate by simply substituting parts on an existing layout.
LTC2170IUKG-12 - 12-Bit 25Msps Quad ADC | Analog Devices
The Analog Devices LTC2170IUKG-12 is a 4-channel, simultaneous-sampling 12-bit analog-to-digital converter (ADC) operating at 25 Msps per channel, housed in a 52-pin QFN (7 mm x 8 mm) package. The part is built on a pipelined architecture and is part of the pin-compatible LTC2172/LTC2171/LTC2170 family, which offers 65 Msps, 40 Msps, and 25 Msps speed grades, allowing designers to scale sampling rate without changing the PCB layout. What is a quad ADC? A quad ADC is an integrated circuit that contains four matched ADC cores and a shared reference, clock, and digital interface. By integrating four converters into one package, the quad ADC removes channel-to-channel timing skew and simplifies PCB routing for multi-channel data acquisition systems. A pipelined ADC converts an analog input by passing the sampled voltage through a cascade of low-resolution stages, producing a high throughput at moderate resolution. Quad ADCs sit inside the hierarchy of data-converter ICs -> ADC -> high-speed ADC -> pipelined ADC -> simultaneous-sampling ADC -> semiconductor. Key features of the LTC2170-12 include 71 dB SNR and 90 dB spurious-free dynamic range (SFDR), 0.15 ps RMS aperture jitter for accurate undersampling of IF signals, and an 800 MHz full-power input bandwidth. The serial LVDS digital interface supports both 1-lane (one bit per channel per cycle) and 2-lane (two bits per channel per cycle) modes, minimizing the number of board traces between the ADC and the FPGA/ASIC. A serial SPI port configures output mode, input range, and channel shutdown. Selectable input ranges of 1 Vp-p to 2 Vp-p enable direct connection to most IF and baseband drivers without external attenuators. Typical applications include multi-channel communications receivers, phased-array antenna digitizers, medical imaging front ends, and industrial ultrasound beamformers. The wide input bandwidth and low jitter also make the part well suited to undersampling of intermediate-frequency signals in software-defined radio (SDR) platforms. When designing with this part, follow the recommended layout in the manufacturer datasheet: keep analog input traces length-matched and surrounded by a continuous ground plane, place the 1.8 V supply decoupling within 5 mm of the ADJ pin, and route the LVDS pairs as 100 ohm differential lines to the FPGA. The exposed pad (EP) on the bottom of the QFN must be soldered to a ground pad for thermal and electrical performance.