EP1SGX40F1020C6 vs EP1SGX40FF1020C7 مقایسه
مقایسه دقیق کنار به کنار EP1SGX40F1020C6 توسط Altera و EP1SGX40FF1020C7 توسط Altera. مشخصات کلیدی، پارامترهای الکتریکی، بسته‌بندی، وضعیت چرخه عمر، قیمت‌گذاری و موجودی را مقایسه کنید تا بهترین قطعه را برای نیازهای طراحی خود تعیین کنید.
Altera
EP1SGX40FF1020C7 - Stratix GX FPGA 41,250 LE | Intel | 1020-BGA
EP1SGX40FF1020C7 ⚠ آخرین فرصت خریدمقایسه مشخصات
| پارامتر | EP1SGX40F1020C6 | EP1SGX40FF1020C7 |
|---|---|---|
| برند | Altera | Altera |
| دسته‌بندی | FPGA & CPLD | FPGA & CPLD |
| وضعیت چرخه عمر | Obsolete | آخرین فرصت خرید |
| Family | Stratix GX | Stratix GX (EP1SGX40) |
| Series | EP1SGX40 | Stratix GX |
| Logic Elements | 41,250 | — |
| Configurable Logic Blocks (CLBs) | 4,125 | — |
| Total RAM Bits | 3,423,744 | — |
| Number of I/O Pins | [DATA_NEEDED: I/O pin count] | — |
| Number of Transceivers | [DATA_NEEDED: transceiver count] | — |
| Max Transceiver Data Rate | 3.1875 Gbps | — |
| Core Voltage (VCCINT) | 1.5 V | — |
| Logic Family | CMOS (SRAM-based LUT) | — |
| Package Type | 1020-ball FBGA (FineLine BGA) | — |
| Package Dimensions | 33 x 33 mm | 33 mm × 33 mm |
| Ball Pitch | 1.00 mm | 1.00 mm |
| دمای کاری | 0 C to 85 C (commercial) | 0 °C to 85 °C (commercial) |
| Configuration Method | SRAM-based (volatile, requires boot device) | — |
| Speed Grade | C6 | 7 (-7, mid-speed) |
| وضعیت RoHS | [DATA_NEEDED: RoHS status] | Compliant |
| Logic Elements (LE) | — | 41,250 |
| Configurable Logic Blocks (CLB) | — | 4,125 |
| Embedded Memory (bits) | — | 3,423,744 |
| User I/O Pins | — | 624 |
| Number of Logic Array Blocks (LAB) | — | 4,125 |
| Number of I/O Banks | — | 12 |
| Core Supply Voltage (VCCINT) | — | 1.425 V to 1.575 V (nominal 1.5 V) |
| Process Technology | — | CMOS |
| بسته‌بندی | — | 1020-ball FC-FBGA (S-PBGA-B1020) |
| نوع نصب | — | Surface Mount |
| Configuration Modes | — | PS, PPS, PPA, JTAG, AS |
| DSP Blocks (9-bit) | — | 176 |
| Transceiver Channels | — | 20 full-duplex 3.1875 Gbps + 14 dedicated full-duplex 1.25 Gbps |
| PLLs | — | 8 enhanced + per-transceiver PLLs |