EP20K400CF672C-8 vs EP20K400CF672I8 مقایسه
مقایسه دقیق کنار به کنار EP20K400CF672C-8 توسط Altera و EP20K400CF672I8 توسط Intel. مشخصات کلیدی، پارامترهای الکتریکی، بسته‌بندی، وضعیت چرخه عمر، قیمت‌گذاری و موجودی را مقایسه کنید تا بهترین قطعه را برای نیازهای طراحی خود تعیین کنید.
مقایسه مشخصات
| پارامتر | EP20K400CF672C-8 | EP20K400CF672I8 |
|---|---|---|
| برند | Altera | Intel |
| دسته‌بندی | FPGA & CPLD | FPGA & CPLD |
| وضعیت چرخه عمر | Obsolete | Obsolete |
| Family | APEX 20K | APEX 20KC |
| Logic Elements | 16,640 | — |
| Typical Gates | 400,000 | — |
| Macros | 1,664 | — |
| Maximum User I/O | 488 | — |
| Number of I/O Banks | [DATA_NEEDED: number of I/O banks] | — |
| Package Type | PBGA-672 (FineLine BGA, 27 x 27 mm, 1.0 mm pitch) | 672-pin FC-FBGA (FineLine BGA) |
| Core Voltage (VCCINT) | 1.8 V nominal (1.71 V to 1.89 V) | — |
| I/O Voltage (VCCIO) | [DATA_NEEDED: VCCIO options] | — |
| Pin-to-Pin Delay (tPD) | 1.78 ns (speed grade -8) | — |
| Speed Grade | -8 | I8 |
| Temperature Grade (C) | Commercial, 0 °C to 85 °C | — |
| Process Technology | 0.15 µm all-layer copper CMOS | 0.15 µm CMOS |
| Embedded Memory Type | ESB (RAM / ROM / CAM) | — |
| Configuration Interface | JTAG (IEEE 1149.1), Passive Serial, Passive Parallel | — |
| JTAG Support | Yes (IEEE 1149.1 boundary-scan) | — |
| نوع نصب | Surface Mount (BGA) | Surface Mount (BGA) |
| وضعیت RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance] |
| سطح MSL | [DATA_NEEDED: MSL level] | [DATA_NEEDED: MSL moisture sensitivity level] |
| Series | — | EP20K400 |
| Manufacturer | — | Intel (formerly Altera) |
| Device Type | — | FPGA - Field Programmable Gate Array |
| Logic Elements / Cells | — | 16,640 |
| System Gates | — | 400,000 |
| Embedded Memory (RAM bits) | — | 212,992 |
| Number of Logic Macros | — | 1664 |
| User I/O Pins | — | 488 |
| Supply Voltage - Core | — | 1.8 V |
| I/O Voltage (MultiVolt) | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| Maximum Internal Frequency | — | 301.21 MHz |
| Operating Temperature (Industrial) | — | -40 °C to +100 °C |
| Configuration Method | — | Passive Serial / Active Serial / JTAG (IEEE 1149.1) |
| PLLs | — | 4 |