EP910DI-35 vs EP910IDI-15 مقایسه

مقایسه دقیق کنار به کنار EP910DI-35 توسط Altera و EP910IDI-15 توسط Altera. مشخصات کلیدی، پارامترهای الکتریکی، بسته‌بندی، وضعیت چرخه عمر، قیمت‌گذاری و موجودی را مقایسه کنید تا بهترین قطعه را برای نیازهای طراحی خود تعیین کنید.

مقایسه مشخصات

پارامتر EP910DI-35 EP910IDI-15
برند Altera Altera
دسته‌بندی FPGA & CPLD FPGA & CPLD
وضعیت چرخه عمر فعال Obsolete
Product Type EPLD (Erasable Programmable Logic Device) —
Family Altera Classic EPLD Classic EPLD
Macrocells 24 24
Usable Gates 450 —
Propagation Delay (tPD) 35 ns —
Maximum Toggle Frequency (fCNT) 28.6 MHz —
Supply Voltage (VCC) 4.75 V to 5.25 V (5 V nominal) —
Supply Current (ICC) 40 mA typical —
Dedicated Inputs 10 —
Bidirectional I/O Pins 20 —
Total Pins 40 —
بسته‌بندی CDIP-40 (Ceramic DIP with UV window) 40-pin CDIP (CerDIP) with quartz window
نوع نصب Through-Hole Through-hole (DIP)
دمای کاری -40C to +85C (industrial) -40C to +85C (industrial, "I" grade)
Technology CMOS, UV-erasable EPROM CMOS EPROM
Programming Method EPROM programmer + JEDEC fuse map —
Erasure Method UV light through quartz window —
وضعیت RoHS [DATA_NEEDED: RoHS status - ceramic CDIP legacy parts are typically non-compliant unless specified] [DATA_NEEDED: RoHS compliance of CDIP windowed part]
Logic Family PAL-type AND/OR array with D flip-flops —
Manufacturer Original Altera; long-term authorized by Rochester Electronics, LLC —
Device Type — CPLD (Complex Programmable Logic Device)
Logic Gates — 450 gates
Maximum User I/O Pins — 36
Pin-to-Pin Propagation Delay (tpd) — 15 ns
Maximum Counter Frequency — 66.6 MHz
Supply Voltage (Vcc) — 5 V
Program/Erase Method — UV-erasable windowed CerDIP
Macrocells Configurable As — D, T, JK, SR flip-flop, or combinatorial
Development Tool — MAX+PLUS II (legacy) / Altera Classic compiler
Programming Hardware — Altera Logic Programmer card
Logic Family Compatibility — Pin-, function-, and JEDEC-map compatible across all EP910 speed grades and packages

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