FPGA & CPLD
Produits (6666)
EP20K400EBC652-1 - APEX-20KE FPGA, 400K Gates, 488 I/O, 652-BGA | Altera
The Altera EP20K400EBC652-1 is a member of the APEX-20KE family of Field Programmable Gate Arrays (FPGAs) integrating 400,000 system gates and 488 user I/Os in a 652-ball BGA package operating at a 1.8V core supply. It combines a MultiCore architecture with look-up table (LUT) logic, embedded memory blocks, and a system-on-a-programmable-chip (SOPC) integration fabric for high-density programmable logic designs. The device supports a propagation delay of approximately 2.5 ns per logic element and operates across a commercial 0C to 85C temperature range, making it suitable for high-performance industrial and telecommunications systems. An FPGA (Field Programmable Gate Array) is a type of integrated circuit whose internal logic blocks, routing, and I/O cells are user-defined after manufacture, enabling designers to implement custom digital logic, glue logic, bus bridges, DSP datapaths, and even full soft-processor systems. FPGAs sit at the top of the programmable-logic hierarchy (FPGA > CPLD > PLD > programmable logic) and are used whenever time-to-market, field reconfigurability, or per-unit logic density cannot be served by a fixed ASIC. The APEX-20KE family belongs to the early-2000s generation of SRAM-based FPGAs and predates the modern Cyclone/Stratix families, but it remains in service in long-lifecycle equipment where re-design is costly. Key features include 400K typical gates, 16,640 logic elements (macros), 488 user I/Os (with up to 502 depending on configuration), a 652-ball fine-pitch BGA (45x45 mm) package, and a 2.5V I/O supply with 1.71V to 1.89V core supply range. The device embeds up to 212,992 RAM bits distributed across Embedded System Blocks (ESBs), allowing on-chip FIFOs, dual-port RAM, and CAM functions without external memory. Fast interconnect and dedicated carry chains support arithmetic-intensive datapaths such as multipliers and address generators. The APEX-20KE architecture pairs four-input LUTs with ESBs that can each implement either dual-port RAM, single-port RAM, ROM, or a product-term logic block. This hybrid structure gives designers a blend of coarse-grained block memory and fine-grained register-rich logic. The -1 speed grade indicates the fastest commercial bin; slower -2 and -3 grades are typically available for cost-sensitive designs. Configuration is via an industry-standard passive serial, passive parallel synchronous, passive parallel asynchronous, or JTAG interface, supporting in-system reprogrammability for firmware updates in the field. Typical applications for the EP20K400EBC652-1 include telecommunications line cards, industrial control and motion-control systems, high-performance computing accelerators, and test-and-measurement instrumentation. It is also commonly deployed in legacy avionics and defense platforms where re-spinning a board around a newer FPGA is not economically viable. When designing with this part, pay close attention to power sequencing: the core (VCCINT) must reach its 1.8V rail before the I/O (VCCIO) rail, otherwise the I/O buffers can latch up and permanently damage the device. Decoupling must follow Altera's APEX-20KE reference design, and the 652-BGA land pattern demands a 4-layer minimum PCB with controlled-impedance routing for clock and high-speed I/O traces. This page synthesizes distributor pricing, same-package alternatives, and practical design notes not found in the manufacturer datasheet, giving engineers a one-stop reference for sourcing and applying the EP20K400EBC652-1.
EP20K400EBC652-1X - 400K Gate APEX 20KE FPGA, 652-BGA | Intel
The Intel (formerly Altera) EP20K400EBC652-1X is a member of the APEX 20KE family of Field-Programmable Gate Arrays (FPGAs), delivering approximately 400,000 system gates in a 652-ball BGA package. Built on a 0.22 µm CMOS process, the device integrates 16,640 logic elements, 212,992 bits of embedded memory, and 488 user I/Os. It is fabricated for a 1.8 V core supply with 2.5 V I/O compatibility, and is rated for commercial operating temperatures of 0 °C to 85 °C. The -1X speed grade places it in the faster bin of the APEX 20KE family, targeting design frequencies in the 200–300 MHz range for internal logic paths. An FPGA (Field-Programmable Gate Array) is a semiconductor device containing an array of configurable logic blocks (CLBs), programmable interconnect, and dedicated I/O cells that the designer can wire up after manufacture using an SRAM configuration bitstream. APEX 20KE belongs to the broader taxonomy: programmable logic device -> CPLD/FPGA -> SRAM-based FPGA -> high-density system-on-a-programmable-chip (SOPC) platform. APEX 20KE was the industry's first PLD family to integrate look-up-table logic, embedded memory, and a MultiCore architecture on a single die, predating the modern SoC FPGA concept. Key features of the EP20K400EBC652-1X include four MultiCore elements per row pair combining logic and embedded system blocks (ESBs), on-chip memory expandable to 212 Kbits per ESB group, dedicated clock management and PLLs, JTAG-based IEEE 1149.1 boundary-scan support, and multi-voltage I/O support that interfaces with 1.8 V, 2.5 V, 3.3 V, and 5 V buses through configurable I/O standards. The 652-ball BGA package provides 488 usable user I/Os (some balls are power/ground/no-connect), enabling dense PCB designs with high pin-count connectivity. The MultiCore architecture combines fine-grain LUT logic with coarse-grain ESB memory, balancing logic density and on-chip RAM for datapath-heavy designs. Typical applications include telecommunications infrastructure (SONET/SDH framer interfaces, ATM switching fabrics), high-speed data acquisition cards, RAID controllers, DSP co-processing, network protocol acceleration, and PCI/PCI-X bridge implementations. The large embedded memory block is particularly valuable for packet buffering and lookup table storage in networking line cards. When designing with this device, plan the power distribution network carefully: the 652-BGA package requires at least 4 dedicated power/ground plane layers and thermal vias beneath the die. Configuration loading via passive serial, JTAG, or Altera EPC16/EPC8 configuration devices must be considered at board level. Migration paths exist within the APEX 20KE family (e.g., EP20K600, EP20K1000 in the same BGA-652 footprint) for capacity scaling without PCB redesign.
EP20K400EBC652-2 - APEX-20KE 400K Gates FPGA, 488 I/O | Intel / Altera
The Intel / Altera (formerly Altera) EP20K400EBC652-2 is a 400,000-gate APEX-20KE series Field-Programmable Gate Array (FPGA) housed in a 652-ball BGA package (45x45 mm) with 488 user I/Os and 1.71V to 1.89V core supply. The device features MultiCore architecture combining look-up tables (LUTs) and embedded system blocks (ESBs), enabling system-on-a-programmable-chip (SOPC) integration. According to distributor data, the part targets a propagation delay of approximately 2.5 ns and operates from 0C to 85C. An FPGA (Field-Programmable Gate Array) is a semiconductor device whose digital logic function is defined by user-programmed configuration rather than fixed at the fab. APEX-20KE is a member of the APEX 20K family, which introduced the MultiCore architecture integrating LUTs with embedded memory blocks, putting FPGAs in the broader hierarchy of programmable logic devices (PLDs) and parallel computing accelerators used in digital signal processing, telecom, and embedded systems. Key features include 1664 macrocells (Logic Elements), 488 user I/Os, 212,992 bits of total embedded RAM, 1.71V-1.89V VCCINT core supply, and a 652-ball BGA package that maximizes I/O density for high-bandwidth designs. The APEX-20KE family supports 2.5V supply operation and provides ample embedded memory and logic resources, making it suitable for high-performance glue logic, bus interface bridging, and moderate-complexity datapath acceleration. The APEX-20KE series uses a CMOS process with MultiCore architecture, integrating up to 1664 logic elements with embedded system blocks (ESBs) that can serve as dual-port RAM, ROM, or content-addressable memory. The 652-ball BGA (45x45 mm) is the largest package in the family and is chosen when the design needs maximum I/O, supporting legacy parallel buses and high-pin-count peripherals. Typical applications include telecom line cards, industrial control, ASIC prototyping, and high-density glue logic bridging. The wide 2.5V/3.3V I/O compatibility and large I/O count make it suitable for parallel bus interfaces, video processing pipelines, and pre-silicon validation of complex ASICs. Note that the APEX-20KE family is now in legacy/obsolete status; new designs should consult Intel's current Cyclone or Stratix equivalents. When designing with this FPGA, plan for external configuration memory (EPC or compatible) since the SRAM-based configuration is volatile. Power sequencing must observe the 1.71V-1.89V VCCINT and 2.5V VCCIO ramp requirements, and JTAG access must be brought out for in-system programming and boundary-scan test. This page synthesizes distributor pricing, same-package alternatives, and practical design notes that go beyond the manufacturer datasheet, helping engineers locate drop-in equivalents and verify supply chain availability as of 2026-09-08.
EP20K400EBC652-2X - 400K Gates APEX-20KE FPGA 652-BGA | Altera/Intel
The Altera (Intel) EP20K400EBC652-2X is a high-density APEX-20KE Field-Programmable Gate Array (FPGA) IC delivering 400,000 system gates and 16,640 logic elements in a 652-ball BGA package. Per the manufacturer datasheet family for APEX 20KE, it integrates 212,992 bits of embedded memory, supports up to 488 user I/O pins, and operates from a 1.8V core supply with multi-voltage I/O support. The device uses a 0.22 µm CMOS process technology and is specified for 223 MHz internal performance. An FPGA (Field-Programmable Gate Array) is a programmable logic device from the broader semiconductor category of programmable logic devices (PLDs), which also includes CPLDs and SPLDs. Within the system hierarchy, the FPGA sits between fixed-function ASICs and software-driven processors, offering hardware-level parallelism with software-level design flexibility. The APEX 20KE family pioneered MultiCore integration, combining Look-Up Table (LUT) logic, embedded memory blocks (ESBs), and distributed arithmetic capability in a single fabric to support system-on-a-programmable-chip (SOPC) designs. Key differentiating features include 4 PLLs for clock management, 1,664 logic macrocells, support for multiple I/O standards including LVTTL, LVCMOS, PCI, SSTL, and HSTL, and a dedicated high-speed interconnect called the FastTrack. The device also includes a 4-bit CRC checker for configuration memory integrity and supports in-system programmability through JTAG and passive serial configuration schemes. Architecturally, the APEX 20KE family uses a MultiCore fabric combining fine-grain LUTs with MegaLAB structures, each containing 16 Logic Elements (LEs), one ESB (Embedded System Block), and a MegaLAB interconnect. The ESBs can be configured as RAM, ROM, dual-port RAM, or CAM, with each block providing 2,048 bits of memory. Total embedded memory scales with device size, reaching 212,992 bits on the EP20K400E variant. Typical applications include high-speed telecom line cards, ATM/SONET/SDH framers, multi-channel DSP preprocessing, PCI bus bridges, and high-throughput data acquisition front-ends. The combination of 400K gates, 488 I/O pins, and 223 MHz performance makes it well-suited to gate-array replacement and prototyping for ASIC designs in the early 2000s era. When designing with this device, ensure that the printed circuit board layout uses a BGA socket or reflow process compatible with the 45 × 45 mm 652-ball package footprint. Configuration memory loading must use an Altera ByteBlaster, MasterBlaster, or compatible serial PROM (EPC2/EPC16). Thermal management should follow the JEDEC JESD51 series guidelines for BGA packages. This page synthesizes distributor pricing, drop-in same-package alternatives from the Site MPN list, and practical design notes not found in the original manufacturer datasheet.
EP20K400EBC652-3 - 400K Gates APEX 20KE FPGA 652-BGA | Intel
The Intel (formerly Altera) EP20K400EBC652-3 is an APEX 20KE-series Field Programmable Gate Array (FPGA) housed in a 652-ball BGA package, delivering 400,000 system gates, 16,640 logic elements (cells), and 212,992 bits of embedded memory with 488 user I/Os. The device is built on a 0.22 µm CMOS process with MultiCore™ architecture and operates from a 1.8 V core supply with 2.5 V I/O compatibility, providing a propagation delay of 2.5 ns and system performance up to 213 MHz. An FPGA is a reprogrammable semiconductor device that lets engineers implement custom digital logic by configuring an array of configurable logic blocks (CLBs), embedded memory, and I/O cells. APEX 20KE specifically belongs to the PLD (programmable logic device) family, sitting at the hierarchy FPGA -> programmable logic -> digital IC -> semiconductor. APEX 20KE devices pioneered System-on-a-Programmable-Chip (SOPC) integration by combining look-up-table logic, embedded memory blocks, and high-speed interconnect in a single die. Key differentiating features include the MultiCore™ architecture that integrates look-up tables with embedded dual-port RAM, four dedicated clock pins plus four dedicated fast-input pins driving register control signals for low-skew distribution, and 16,640 cells with 212,992 bits of RAM. The device also supports in-system programmability via the Altera (now Intel) Quartus® toolchain. The BGA-652 footprint with 488 user I/Os (502 user pins per the digchip datasheet summary) makes this device a high-density logic platform for communication, ASIC prototyping, and DSP front-end applications. Technically, the EP20K400EBC652-3 implements an SRAM-based configuration cell array, allowing unlimited reconfiguration through JTAG or configuration EPROMs. The speed grade -3 places it in the moderate-performance tier of the APEX 20KE family, suitable for designs where throughput beyond 100 MHz is not required on every path. The 0.22 µm CMOS process delivers a good balance of density, power, and cost at the expense of the latest low-power nodes. Typical applications include telecommunications infrastructure such as ATM switches and SONET/SDH framer designs, ASIC prototyping for high-complexity glue logic, DSP data-path pre-processing, and bus-interface bridging in industrial backplanes. The 488 user I/Os and 16,640 cells make it suitable for high-bandwidth parallel interfaces. When designing with this part, ensure your power tree delivers clean 1.8 V core and 2.5 V I/O rails with proper decoupling, account for the BGA-652 PCB layout and the BGA escape routing for all four clock pins. Quartus II (legacy) or Quartus Prime can synthesize, place-and-route, and program the device via JTAG or Altera configuration devices. This page consolidates distributor stock, lifecycle data, drop-in variants in the Site MPN list, and design considerations not found in the standalone datasheet, helping engineers verify supply, identify speed-grade substitutions, and select a working APEX 20KE device for legacy designs.
EP20K400EBC652-3N - APEX 20KE FPGA, 400K Gates, 488 I/O BGA | Intel
The Intel (formerly Altera) EP20K400EBC652-3N is a high-density APEX 20KE field-programmable gate array (FPGA) integrating 400,000 system gates with 16,640 logic elements and 212,992 bits of embedded memory, housed in a 652-ball BGA package. It provides 488 user I/O pins, operates from a 1.8 V core supply, and is fabricated on a 0.22 µm CMOS process. The -3N speed grade is the production-grade temperature (0°C to 85°C) tier of the APEX 20KE family. An FPGA (Field-Programmable Gate Array) is a semiconductor device containing configurable logic blocks (CLBs), programmable interconnects, and I/O cells that can be re-programmed after manufacturing to implement arbitrary digital logic. FPGAs occupy a position in the programmable logic hierarchy: PLD -> CPLD -> FPGA -> SoC FPGA. The APEX 20KE family was one of Intel/Altera's MultiCore architecture devices, integrating look-up table (LUT) logic with embedded memory blocks for system-on-a-programmable-chip (SOPC) applications. Key features of the EP20K400EBC652-3N include 16,640 logic elements, 212,992 bits of RAM, support for multiple I/O standards including LVTTL, LVCMOS, PCI, and LVDS, in-system programmability via IEEE 1532 or passive serial configuration, and four phase-locked loops (PLLs) for clock management. The MultiCore architecture integrates LUT-based logic with embedded system blocks (ESBs) that can act as either dual-port RAM, ROM, or content-addressable memory. The device delivers up to 213 MHz internal operation per the manufacturer datasheet and supports true LVDS I/O at data rates suitable for backplane and high-speed serial applications of its era. The 0.22 µm process and 1.8 V core supply were state-of-the-art when the APEX 20KE family was introduced and remain a stable platform for legacy industrial and telecommunications designs. Typical applications include telecommunications switching equipment, high-speed data acquisition, industrial control and automation backplanes, military/aerospace signal processing, and ASIC prototyping. The 488 user I/Os make it well-suited for bus-intensive designs requiring wide parallel interfaces. When designing with the EP20K400EBC652-3N, careful attention must be paid to power sequencing of the 1.8 V core and I/O supply rails, signal integrity on the LVDS pairs, and thermal management of the 652-ball BGA. Configuration is performed through the dedicated JTAG or passive serial interface. This page synthesizes distributor pricing, drop-in pin-compatible same-family variants, and practical design considerations not found in the manufacturer datasheet alone, providing engineers with a complete decision reference for sourcing and replacing the EP20K400EBC652-3N.
EP20K400EBI652-2X - APEX 20K 400K Gates FPGA 652-BGA | Intel
The Intel (formerly Altera) EP20K400EBI652-2X is a high-density APEX 20K family FPGA delivering up to 400,000 system gates with 16,640 logic cells, 1664 logic elements (Macros) and 488 user I/O pins, housed in a 652-ball FineLine BGA package and fabricated on a 0.22 µm CMOS process. The device runs from a 1.8 V core supply, supports system speeds up to 223 MHz, and combines LUT-based logic with embedded system blocks for memory and arithmetic. An FPGA (Field Programmable Gate Array) is a programmable logic device that integrates configurable logic blocks, interconnect, and I/O cells onto a single silicon die. Within the broader taxonomy, the APEX 20K family is classified as a PLD (Programmable Logic Device) -> CPLD/FPGA hybrid -> high-density FPGA -> SRAM-based FPGA -> logic IC. FPGAs are widely used for ASIC prototyping, glue logic, parallel processing pipelines, and interface bridging where fixed-function silicon cannot meet time-to-market or volume economics. Key differentiating features of the EP20K400EBI652-2X include a four-level hierarchical FastTrack interconnect structure for predictable timing closure, embedded system blocks providing distributed dual-port RAM, built-in LVDS support and multi-standard I/O, plus in-system configuration via passive serial, passive parallel, and JTAG modes. The thermally enhanced 652-ball BGA enables higher dissipation headroom than the standard BGA variant, suiting industrial workloads. The APEX 20K architecture combines look-up table (LUT) logic with embedded array blocks (EABs), allowing designers to implement both random logic and on-chip memory in a single device. The high logic-to-pin ratio (488 I/O on 16,640 cells) makes the part efficient for parallel buses, telecommunications backplanes, and high-speed instrumentation front-ends. Typical applications include telecommunications line-card processing, high-speed DSP pre-processing, industrial motion control, video/imaging pipelines, and ASIC prototyping where 400K gates provide adequate headroom for moderately complex designs. Designers should review the Altera Device Package Information Data Sheet for the taller thermally enhanced BGA mechanical outline before committing PCB footprints, and consult Quartus / MAX+PLUS II configuration notes to plan the JTAG or passive serial programming chain. This page synthesizes distributor pricing, drop-in alternatives within the APEX 20K family, and practical design notes not found in the manufacturer datasheet alone.
EP20K400EFC672-1 - APEX 20KE FPGA 400K Gates 672-FBGA | Intel
The Intel (formerly Altera) EP20K400EFC672-1 is a member of the APEX 20KE family of SRAM-based Field Programmable Gate Arrays (FPGAs), delivering up to 400,000 system gates and 16,640 logic elements in a 672-pin FineLine BGA (FC-FBGA) package. It targets high-density, system-on-a-programmable-chip (SOPC) integration with MultiCore architecture combining look-up tables, product-term logic, and embedded memory in a single fabric. An FPGA (Field Programmable Gate Array) is a type of programmable logic device (PLD) that lets designers implement custom digital logic after PCB fabrication. Within the broader semiconductor taxonomy, FPGAs sit above CPLDs and below fixed-function ASICs in design flexibility. The APEX 20KE family was Altera's flagship high-density platform before the Stratix era, and was widely adopted for telecom, networking, and DSP prototyping designs of the late 1990s and early 2000s. Key features of the EP20K400EFC672-1 include 488 user I/O pins, up to 212,992 bits of embedded SRAM, a 1.8V core supply with 2.5V/3.3V tolerant I/O, and support for multiple I/O standards including LVTTL, LVCMOS, PCI, SSTL, and HSTL. The -1 speed grade corresponds to a 368 MHz internal operation. The MultiCore architecture integrates LUT-based logic, embedded array blocks (EABs) for memory, and product-term logic for fast register-intensive functions. Typical applications include high-speed telecommunications backplanes, ASIC prototyping, digital signal processing pipelines, network switching fabrics, and embedded control systems where hundreds of thousands of gates are needed without the NRE cost of an ASIC. The device supports in-system programmability via JTAG and Altera's MAX+PLUS II or Quartus design flows. When designing with the EP20K400EFC672-1, careful PCB layout is critical because the 672-ball FC-FBGA package requires microvia technology and controlled-impedance routing. Engineers should provide multiple decoupling capacitors near the balls, follow Intel/Altera's reference decoupling guidelines, and validate signal integrity on high-speed I/O using IBIS models. This page synthesizes current distributor pricing, drop-in same-brand alternatives, and engineering context not found in the original manufacturer datasheet, helping procurement and design engineers make informed lifecycle decisions.
EP20K400EFC672-1N - 400K Gates APEX 20KE FPGA, BGA-672 | Intel
The Intel EP20K400EFC672-1N is a high-density APEX 20KE family FPGA integrating 400,000 system gates and 16,640 logic cells in a 672-ball fine-pitch BGA (FC-FBGA) package. Built on a 0.22 µm CMOS process, the device delivers up to 368 MHz core performance and supports MultiCore™ architecture combining look-up tables (LUTs), product-term logic, and embedded memory blocks for true system-on-a-programmable-chip (SOPC) integration. The part operates from a 1.8 V core supply with a 2.5 V I/O supply and offers 502 user I/Os (488 user I/Os per Mouser listing). Industrial-grade temperature range spans 0 °C to 85 °C, and propagation delay is rated at 2.5 ns. An FPGA (Field-Programmable Gate Array) is a reconfigurable semiconductor containing programmable logic blocks, interconnect, and I/O cells that engineers can program post-manufacture to implement custom digital circuits. Within the broader hierarchy, FPGAs sit between general-purpose microcontrollers and application-specific integrated circuits (ASICs), offering hardware-level parallelism with software-like design flow. The APEX 20KE series is Intel's (formerly Altera's) MultiCore architecture family that combines four architectural elements - LUTs, product-term logic, embedded array blocks (EABs), and FastTrack interconnect - to support both register-rich datapaths and memory-intensive functions on one die. Key features of the EP20K400EFC672-1N include 16,640 logic elements, 502 user I/Os, 4 PLLs for clock management, embedded system blocks, and dedicated double-data-rate (DDR) support. The MultiCore architecture lets designers allocate logic between look-up table regions and embedded array blocks, optimizing for either combinational density or on-chip memory. The device supports in-system programmability via the IEEE 1149.1 JTAG interface, allowing configuration refresh without removing the part from the board. Typical applications include high-speed digital signal processing, telecommunications backplane interfaces, protocol bridging, custom peripheral controllers, and ASIC prototyping. The 400K-gate density suits designs that have outgrown smaller CPLDs but do not yet require a structured ASIC NRE investment. Designers typically target APEX 20KE for glue-logic aggregation, bus interface conversion, and pre-silicon validation of next-generation ASICs. When designing with this FPGA, plan power sequencing for the 1.8 V VCCINT before the 2.5 V VCCIO rail to avoid I/O latch-up. Verify JTAG chain integrity during bring-up, and use Intel's Quartus II design suite (the legacy toolchain for APEX 20KE) for synthesis, place-and-route, and timing closure. The part is also available in the EFC672-1N speed/temperature grade; alternative grades include -1X (extended temp) and -2 (faster speed). This page synthesizes distributor pricing, drop-in alternative listings from the same Intel APEX 20KE family, and practical design notes not found in the legacy APEX 20KE datasheet, giving engineers a faster path to BOM decisions on legacy Altera silicon.
EP20K400EFC672-1XN - APEX 20KE FPGA, 400K Gates, 672-BGA | Intel
The Intel EP20K400EFC672-1XN is a high-density APEX-20KE Field Programmable Gate Array (FPGA) delivering 400K system gates, 16,640 logic elements, and 212,992 bits of embedded RAM in a 672-ball FineLine BGA (FC-FBGA) package. It operates from a 1.8 V core supply and is built on a 0.18 µm CMOS process with 1.5 V I/O standards supported through MultiVolt I/O technology. An FPGA (Field Programmable Gate Array) is a reprogrammable integrated circuit composed of an array of configurable logic blocks (CLBs), programmable routing, and embedded memory and DSP resources. FPGAs sit within the broader semiconductor hierarchy as programmable logic devices (PLDs) between fixed-function ASICs and software-defined processors. They are widely used for parallel data processing, custom I/O interfaces, and hardware acceleration in applications requiring deterministic latency or high I/O bandwidth. The APEX-20KE family extends the APEX 20K architecture with enhanced embedded memory and MultiVolt support, making it suitable for bridging multiple logic interfaces on a single board. Key features of the EP20K400EFC672-1XN include 1,664 logic array blocks (LABs), 488 user I/O pins, 4 embedded PLL (phase-locked loop) blocks for clock management, and ESB (Embedded System Block) memory supporting dual-port RAM, ROM, and FIFO configurations. The device supports up to four configuration modes, including passive serial, passive parallel, and JTAG, enabling flexible in-system programming via IEEE 1149.1 boundary scan. Architecturally, the EP20K400EFC672-1XN combines look-up table (LUT)-based logic with dedicated carry chains, embedded multiplier blocks (in the 'E' series), and an enhanced interconnect fabric. The high gate count combined with 488 user I/Os makes it suitable for data-path-intensive designs that require a large number of external interfaces and parallel processing paths. Typical applications include telecom backplane bridging, high-speed serial protocol bridging, industrial control systems, custom DSP preprocessing, and ASIC prototyping. The wide I/O count supports legacy parallel bus standards such as PCI, and the embedded PLLs enable multiple clock-domain synthesis for SoC prototyping. When designing with this device, ensure that the 672-ball BGA fan-out is achievable on the target PCB stack-up; high-density BGAs typically require at least 6 PCB layers with microvia technology for reliable assembly. The Quartus design suite provides pre-built IP cores including DDRx controllers and PLL macros. This page consolidates distributor stock levels, parametric cross-references, drop-in alternative candidates, and design considerations that complement the manufacturer datasheet for the EP20K400EFC672-1XN.
EP20K400EFC672-2 - 400K Gates APEX 20KE FPGA | Intel / Altera
The Intel / Altera EP20K400EFC672-2 is a high-density APEX 20KE Field Programmable Gate Array (FPGA) from the APEX-20KE family, delivering 400,000 system gates and 16,640 logic elements in a 672-ball FineLine Ball Grid Array (FC-FBGA) package. The device operates at a core voltage of 1.8V with 488 user I/Os and a propagation delay of approximately 2.5 ns, making it suitable for high-performance logic integration in mid-2000s-era telecom, networking, and DSP applications. Its MultiCore architecture combines look-up tables (LUTs), embedded system blocks (ESBs) for memory, and product-term logic on a single die. An FPGA (Field Programmable Gate Array) is a type of programmable logic device (PLD) that allows engineers to implement custom digital circuits by configuring an array of configurable logic blocks (CLBs), interconnect, and I/O cells after manufacturing. FPGAs sit hierarchically between simple programmable logic (CPLDs) and fixed-function ASICs, offering higher logic density than CPLDs but lower per-unit cost than full ASICs at low volumes. APEX 20KE devices extend the original APEX 20K family by adding MultiCore interconnect and embedded memory, occupying the high-density tier within Altera's programmable logic portfolio at the time of release. Key features of the EP20K400EFC672-2 include 212,992 bits of embedded RAM, 488 maximum user I/Os, a 1.8V core supply with 2.5V tolerant I/O support, and a commercial operating temperature range of 0C to 85C. The FC-FBGA-672 package provides a 1.0 mm ball pitch, supporting high-pin-count designs with controlled impedance signal integrity. The device supports in-system programmability via JTAG and configuration via serial or parallel PROM interfaces, and was widely used in designs that required rapid prototyping before ASIC conversion. The APEX 20KE architecture integrates four types of logic structures: LUTs for register-intensive datapaths, product-term logic for control state machines, ESBs that can act as dual-port RAM, ROM, or CAM, and a high-bandwidth MultiCore interconnect that ties the structures together. This heterogeneous fabric allowed designers to place LUT-based and product-term logic in the same device without sacrificing utilization, an advantage over pure LUT-based FPGAs of that generation. Typical applications for the EP20K400EFC672-2 include telecommunications line cards, baseband processing in early 3G infrastructure, networking switches and routers, custom DSP pipelines, and PCI bus interface bridging. The high I/O count and embedded memory made it well-suited for packet processing engines and protocol conversion functions where multiple parallel interfaces had to be absorbed on a single device. When designing with this device, engineers should note that APEX 20KE parts have reached end-of-life status from Intel/Altera, and new designs should target Cyclone, Arria, or Stratix families. Existing designs should consider lifetime-buy planning and verify that the Quartus II design software version (13.0 SP1 or earlier for APEX support) is still available in the engineer's design flow. This page synthesizes distributor pricing, lifecycle status, drop-in alternatives from the same APEX 20KE family, and practical design notes that complement the official APEX 20KE datasheet from Altera. All specifications are cross-referenced against DigiKey, Mouser, and Octopart listings as of 2026-09-08.
EP20K400EFC672-2N - APEX 20KE 400K Gates FPGA 672-FBGA | Intel
The Intel / Altera EP20K400EFC672-2N is a member of the APEX 20KE family of programmable logic devices (PLDs) integrating 400,000 system gates, 16,640 logic elements (cells), and 488 user I/Os into a 672-pin Fine-pitch Chip-Scale Ball Grid Array (FC-FBGA) package. It is fabricated on a 0.22 um CMOS process, operates from a 1.8 V core supply with 2.5 V supply reference, and is specified for commercial operating temperature 0 to +85 C with internal propagation delay of 2.5 ns. An FPGA (Field-Programmable Gate Array) is a semiconductor device containing an array of configurable logic blocks (CLBs), programmable interconnects, and I/O cells that can be re-programmed to implement arbitrary digital logic. APEX 20KE belongs to Intel/Altera's MultiCore architecture family which integrates look-up table (LUT) logic with embedded memory blocks (ESBs), placing it within the broader hierarchy: programmable logic device -> CPLD/FPGA -> system-on-a-programmable-chip (SOPC) platform. Key features include 212,992 system gates equivalent capacity (per manufacturer ordering information), four-phase PLL clock management for on-chip clock synthesis, and embedded system blocks (ESBs) for distributed SRAM. The MultiCore architecture combines fine-grained LUT logic with coarse-grained embedded array blocks (EABs), enabling both data-path and control logic on a single die. The device supports in-system programmability via IEEE 1149.1 JTAG and serial configuration schemes. Typical applications include high-speed data processing prototypes, telecommunications line cards, industrial automation controllers, and rapid prototyping of digital signal processing pipelines. The 672-ball FBGA package provides ample signal integrity headroom for DDR memory interfaces and multi-channel LVDS signalling. Designers should use the Altera Quartus II design suite (legacy) for place-and-route and timing closure. Power sequencing of the 1.8 V VCCINT and 2.5 V VCCIO rails must follow Altera's APEX 20KE reference design to avoid JTAG configuration failures. Note that APEX 20KE is a mature, NRND/EOL family; long-lead-time orders should be confirmed with authorized distributors. This page synthesizes distributor pricing, drop-in pin-compatible alternatives, and practical design notes for the EP20K400EFC672-2N that are not consolidated on the legacy Altera datasheet, accelerating BOM validation and procurement decisions.
EP20K400EFC672-2X - APEX 20KE FPGA 400K Gates 672-BGA | Intel
The Intel (formerly Altera) EP20K400EFC672-2X is a member of the APEX-20KE family of high-density SRAM-based Field Programmable Gate Arrays, integrating 400,000 system gates, 16,640 logic elements, and 212,992 bits of embedded RAM in a 672-ball Fine-Pitch Ball Grid Array (FC-FBGA / BBGA) package. Built on a 0.18-micron CMOS process, the device operates from a 1.71 V to 1.89 V core supply and provides 488 user I/Os, making it one of the highest-density programmable logic devices of its generation. A Field Programmable Gate Array (FPGA) is a semiconductor integrated circuit that can be configured by the customer or designer after manufacturing. Architecturally, an FPGA sits within the broader hierarchy of programmable logic devices (PLDs) -> complex programmable logic devices (CPLDs) -> FPGAs -> SRAM-based FPGAs -> APEX-20KE family. The APEX-20KE architecture combines look-up tables (LUTs) with embedded memory blocks (ESBs) and supports MultiCore integration, which was industry-leading when introduced as one of the first PLDs marketed as a "system-on-a-programmable-chip" (SOPC) building block. Key features of the EP20K400EFC672-2X include 1,664 logic array blocks (LABs), 488 maximum user I/Os, 212,992 total RAM bits distributed across embedded system blocks, a MultiCore architecture combining LUT-based logic with dual-port RAM, and 4-phase PLL clock management. The "-2X" speed grade designates a faster speed bin than the standard -2 grade; the part operates at junction temperatures between 0 C and 85 C (commercial grade). Typical applications for the EP20K400EFC672-2X span telecommunications backplanes, industrial automation controllers, high-performance DSP preprocessing, and glue-logic aggregation where high gate count and abundant I/O outweigh the need for the latest process node. Because the APEX-20KE family predates Cyclone and Stratix, designers typically use it only as a long-life mature node or as a second-source drop-in for legacy designs. When designing with this FPGA, ensure the 1.8 V core and 3.3 V I/O supply rails are properly decoupled near the BGA balls with low-ESR ceramic capacitors. Programming is performed via the Altera ByteBlaster or USB-Blaster download cable through the JTAG or passive serial interface; configuration bitstreams are stored in external PROMs or flash. This page synthesizes distributor pricing, drop-in same-package alternatives, and practical design notes that go beyond the original datasheet.
EP20K400EFC672-3 - 400K Gate APEX-20KE FPGA 672-BBGA | Intel
The Intel (Altera) EP20K400EFC672-3 is a high-density APEX-20KE Field Programmable Gate Array (FPGA) IC delivering 16,640 logic elements (approximately 1,052,000 gates), 212,992 bits of embedded RAM, and 488 user I/Os in a 672-ball FineLine BGA package with a -3 speed grade. An FPGA (Field Programmable Gate Array) is a semiconductor device built around an array of configurable logic blocks (CLBs), embedded memory, and programmable interconnect that the user can redefine after manufacture. APEX-20KE belongs to the APEX (Advanced Logic Element Matrix) family and was Altera's first System-On-a-Programmable-Chip (SOPC) architecture, integrating look-up-table (LUT) based logic with embedded dual-port RAM and True-LVDS support so that complex glue-logic, datapath, and bus-interface functions can be consolidated into a single device. Key features of the EP20K400EFC672-3 include 488 maximum user I/Os, 1.8 V core supply with 2.5 V multi-voltage I/O support, on-chip PLL clock management, LVDS/True-LVDS compatible I/O pairs, and MultiCore architecture that combines fine-grained LUTs with embedded memory blocks (ESBs). The -3 speed grade denotes the fastest commercial-grade speed bin in this family and pairs with a 0 to 85 C operating temperature window. Architecturally, the device embeds 212 Kbits of distributed SRAM organized as embedded system blocks, each capable of true dual-port operation. Combined with dedicated multiplier/carry chains and high fan-out routing, the EP20K400 supports high-bandwidth datapath designs, bus interfaces (PCI, SDRAM), and protocol bridging on a single die. The 672-ball FineLine BGA provides controlled-impedance signal integrity for high-speed parallel buses. Typical applications include telecommunication line cards, industrial control and automation, networking switches/routers, and ASIC prototyping/emulation. APEX-20KE was widely adopted in mid-2000s designs and remains available as a long-lifecycle part for industrial and military refresh programs. Design consideration: ensure I/O bank supply voltages match the connected logic (3.3 V, 2.5 V, 1.8 V). Add decoupling on every VCCINT/VCCIO pin and verify JTAG chain integrity before in-system programming. This page synthesizes distributor inventory, same-package alternatives, and design context not found in the original datasheet.
EP20K400EFC672-3N - APEX 20KE 400K FPGA, 488 I/O | Intel / Altera
The Intel / Altera EP20K400EFC672-3N is a member of the APEX 20KE family of Field Programmable Gate Arrays (FPGAs) that delivers 400,000 system gates, 16,640 logic elements, and 212,992 bits of embedded RAM in a 672-pin FC-FBGA (Fine-pitch Chip-scale Fine-pitch Ball Grid Array) package. It exposes 488 user I/O pins, supports LVCMOS/LVTTL/LVDS/PCI interfacing, and operates from a 1.71 V to 1.89 V core supply with a propagation delay of 2.5 ns at speed grade -3. A Field-Programmable Gate Array (FPGA) is a type of integrated circuit whose logic fabric, interconnect, and I/O cells can be reconfigured after manufacture by the end user. The APEX 20KE device family introduced Altera's MultiCore architecture, which integrates look-up table (LUT) logic, embedded system blocks (ESBs) for dual-port RAM/ROM, and high-speed I/O on a single die - effectively an early System-on-a-Programmable-Chip (SOPC) platform. Within the broader taxonomy, this places FPGAs under Programmable Logic Devices (PLD) > CPLD/FPGA > Integrated Circuit > Semiconductor. Key feature highlights include the MultiCore architecture combining LUT-based logic with embedded array blocks, 4 PLLs for clock management, True-LVDS support, and a 1.05M-system-gate density ceiling. The device supports in-system programmability via serial configuration and is offered with both commercial (0 °C to +85 °C) and industrial temperature grades. Speed grade -3 is the second-fastest of the APEX 20KE family, with -2, -1, and -X slower options also available. Typical applications for the EP20K400EFC672-3N include high-performance digital signal processing, telecom baseband processing, networking line cards, and embedded control platforms where mid-1990s to early-2000s design ecosystems still remain in service. The combination of substantial embedded memory and abundant I/O makes it well suited for parallel datapath and protocol-bridging designs. When designing with this part, verify the exact package footprint (FC-FBGA-672) against the PCB land pattern and confirm configuration interface voltage compatibility with the selected PROM or processor. Note that the APEX 20KE family has been classified NRND/EOL by Intel in favor of newer Cyclone/Arria series, so lifecycle planning and last-time-buy inventory strategy are critical. This page synthesizes distributor pricing, pin-compatible drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone, including comparison with related APEX 20KE speed grades and the same-density EFC672 footprint across speed bin -2 and -1.
EP20K400EFI672-2N - APEX-20K FPGA 16640 LEs 488 I/O FBGA-672 | Altera / Intel
The Altera (now Intel) EP20K400EFI672-2N is a member of the APEX-20K® family of CMOS Field-Programmable Gate Arrays (FPGAs), delivering 16,640 logic elements, 212,992 bits of embedded RAM, and 488 user I/O pins in a 672-ball Fine-pitch BGA (FCBGA) package measuring 27 mm x 27 mm. It targets high-density, high-performance glue-logic and co-processing applications in telecom, networking, and DSP acceleration. Operating from a 1.71 V to 1.89 V core supply (VCCINT) and supporting up to 1,052,000 equivalent gates of logic capacity, the EP20K400 integrates 1,664 Logic Array Blocks (LABs) and 488 maximum user I/O pins arranged across multiple I/O banks. An FPGA (Field-Programmable Gate Array) is a type of integrated circuit whose digital logic function is defined after manufacture, allowing designers to program arbitrary combinational and sequential logic using hardware description languages (HDL) such as Verilog or VHDL. FPGAs occupy a position in the digital design hierarchy between fixed-function ASICs (which are cheaper in volume but cannot be modified) and microcontrollers (which run software but offer lower throughput). The APEX-20K family specifically introduced MultiCore™ architecture combining lookup tables (LUTs), embedded memory, and dedicated carry/ cascade chains for arithmetic-intensive designs. Key features of the EP20K400EFI672-2N include the integrated 212,992-bit embedded SRAM distributed across the logic array, four phase-locked loops (PLLs) for clock management, and support for multiple I/O standards including LVTTL, LVCMOS, PCI, and LVDS via configurable I/O banks. The device supports in-system programmability via IEEE 1149.1 (JTAG) and Altera's passive serial/active serial configuration schemes. The industrial-grade operating range of -40 °C to +100 °C junction temperature makes it suitable for harsh-environment embedded systems. Architecturally, the EPEX-20K family combines fine-grained logic elements with embedded memory blocks, allowing true dual-port RAM implementations and FIFOs without consuming logic resources. The device supports multi-voltage I/O operation, allowing 3.3 V, 2.5 V, and 1.8 V interfaces simultaneously across separate I/O banks with level-shifting handled internally. This makes the EP20K400 particularly well-suited for bridging legacy 5 V-tolerant peripherals with modern low-voltage processors on the same board. Typical applications include high-speed data-path bridging, telecommunications line-card glue logic, DSP co-processing front-ends, ATM/SONET framer interfaces, and PCI-to-PCI bridge implementations. The 488 user I/Os make it useful for parallel bus aggregation in legacy industrial control systems and as a pre-processing stage for image or video pipelines. When designing with the EP20K400EFI672-2N, engineers must provide a stable 1.8 V core supply with adequate decoupling and respect the in-rush current profile during configuration. The FCBGA-672 package requires careful PCB stack-up design to route signals out of the dense 1.0 mm pitch ball grid without compromising signal integrity. This page synthesizes distributor pricing, lifecycle status, drop-in alternatives drawn from the Altera APEX-20K family, and practical design notes not aggregated on any single manufacturer or distributor page.
EP20K400EFI672-2X - 400K-Gate APEX 20KE FPGA, 672-FBGA | Intel
The Intel (formerly Altera) EP20K400EFI672-2X is a member of the APEX 20KE family of Field Programmable Gate Arrays (FPGAs) housed in a 672-ball FineLine BGA (FC-FBGA) package, integrating 400,000 system gates, 16,640 logic elements (LEs) and 212,992 bits of embedded memory, with 488 user I/O pins and a 1.8 V core supply. The device is fabricated on a 0.22 µm CMOS process and supports internal performance up to 223 MHz, making it suitable for high-density system-on-a-programmable-chip (SOPC) designs that combine lookup-table (LUT) logic, embedded array blocks (EABs) and distributed memory in a single MultiCore architecture. An FPGA (Field Programmable Gate Array) is a type of programmable logic device (PLD) that allows designers to configure logic resources and interconnects after manufacturing. Within the broader semiconductor taxonomy, FPGAs sit between standard logic ICs and ASICs: more flexible than fixed-function chips but lower per-unit cost than full-custom ASICs at low volumes. The APEX 20KE family specifically introduced MultiCore architecture that pairs fine-grain LUT logic with coarse-grain EAB memory, enabling SOPC integration of processors, memory and I/O on a single programmable fabric. Key features of the EP20K400EFI672-2X include 16,640 logic elements organized into Logic Array Blocks (LABs), 212,992 bits of RAM, 480 LVTTL/LVCMOS-compatible I/O organized into 8 I/O banks, four Phase-Locked Loops (PLLs) for clock management, and support for multiple I/O standards including LVTTL, LVCMOS, PCI and GTL+. The part is specified for the industrial 0 °C to 85 °C operating temperature range with a 1.71 V to 1.89 V core supply tolerance. Technically, the MultiCore architecture allows each logic element to operate as a 4-input LUT, a 16-bit shift register, or a small memory block, while EABs provide up to 2,048 bits each of synchronous dual-port RAM, ROM or content-addressable memory. The four embedded PLLs multiply, divide and phase-shift incoming clocks up to 223 MHz, eliminating off-chip clock generators in many designs. The 672-pin FineLine BGA package is a 27 mm × 27 mm FC-FBGA with 1.27 mm pitch that supports high-speed board designs with controlled-impedance signal paths. Typical applications include telecommunications line cards, industrial control and automation backplanes, high-speed data-acquisition front-ends, military/aerospace signal processing prototypes, and PCI-based I/O expansion cards. The combination of 488 user I/Os and 212,992 bits of embedded memory makes it well suited to designs that previously required a separate controller ASIC plus a discrete logic FPGA. Designers often pair the EP20K400EFI672-2X with external SDRAM and a microprocessor for embedded compute platforms. When designing with this device, allocate at least 20 % of logic utilization as headroom for place-and-route closure, and verify that LVTTL/LVCMOS drive strength is matched to each signal path. Power sequencing requires VCCINT (1.8 V) to ramp before VCCIO to prevent I/O latch-up; consult the APEX 20KE datasheet for the recommended sequencing diagram. The part is in the mature/end-of-life phase of its lifecycle - confirm long-term availability with Intel/Altera distributors before committing to new designs. This page synthesizes distributor pricing, drop-in APEX 20KE alternatives, comparison tables and design notes that are not found in a single datasheet, helping engineers quickly decide whether the EP20K400EFI672-2X fits their high-density programmable-logic application.
EP20K400FC672-1XGZ - 400K Gate APEX-20KE FPGA, 502 I/O, 672-FBGA | Intel
The Intel (formerly Altera) EP20K400FC672-1XGZ is a high-density APEX-20KE Field-Programmable Gate Array (FPGA) in the 672-pin Fine-Pitch Ball Grid Array (FBGA) package, integrating approximately 400,000 system gates with up to 502 user I/O pins. Per the manufacturer product listing, this device belongs to the APEX-20KE family and features the MultiCore architecture combining embedded system blocks (ESBs) for memory and logic fabric. A Field-Programmable Gate Array (FPGA) is a type of programmable logic device (PLD) that uses configurable logic blocks (LUTs), programmable interconnects, and dedicated I/O cells to implement arbitrary digital circuits after PCB assembly. APEX-20KE sits in the hierarchy: APEX-20KE -> APEX 20K family -> programmable logic -> CMOS ASIC-replacement IC. The 2.5V core supply and CMOS process technology place it in the older high-density programmable logic generation, predating modern 28nm/14nm FPGAs but still widely deployed in long-lifecycle industrial and communications equipment. Key features of the EP20K400FC672-1XGZ include 16,640 logic elements/cells, a propagation delay of 2.5 ns, and 212,992 bits of embedded memory. The 672-FBGA package exposes 502 general-purpose I/O pins supporting multiple I/O standards (LVTTL, LVCMOS, PCI, GTL+) per the APEX-20KE datasheet family. The -1 speed grade denotes the slowest commercial speed bin (compared to -2 and -3 grades), trading timing margin for cost. Technically, the APEX-20KE combines look-up-table-based logic elements with embedded system blocks that can be configured as dual-port RAM, ROM, or content-addressable memory. The MultiCore architecture allows the embedded memory and logic fabric to be sized independently for each design, and the deterministic interconnect fabric supports high-speed datapath placement for DSP, telecom, and glue-logic functions. Typical applications include telecommunications backplane glue logic, industrial control and factory automation controllers, network routers and switches, DSP coprocessing, and legacy ASIC replacement in long-lifecycle military and avionics systems. Engineers choose APEX-20KE specifically for designs that must remain bit-identical with installed OEM equipment, where migration to a newer FPGA family would require extensive re-validation. A critical design consideration when using the EP20K400FC672-1XGZ is power-rail sequencing and I/O bank VCCIO configuration - mis-setting bank voltages can cause permanent damage to I/O buffers. Always use Altera Quartus II (legacy) or equivalent programming tools and follow the JTAG configuration sequence in the APEX-20KE handbook. This page synthesizes distributor availability, drop-in APEX-20K family alternatives, and practical design guidance not found in the manufacturer datasheet alone.
EP20K400FC672-2 - 400K Gates APEX-20K FPGA, 502 I/O | Intel
The Intel (formerly Altera) EP20K400FC672-2 is a high-density APEX-20K Field Programmable Gate Array (FPGA) fabricated on a 0.22 µm CMOS process, delivering 400,000 system gates and 16,640 logic elements in a 672-ball FineLine BGA (FC-FBGA) package. It integrates 502 user I/O pins, 212,992 bits of embedded memory, and operates at up to 200 MHz core frequency from a 2.5 V supply with 2.5 ns propagation delay. An FPGA (Field Programmable Gate Array) is a reprogrammable semiconductor device that combines configurable logic blocks (CLBs), programmable interconnects, and I/O cells on a single die. The APEX-20K family pioneered the MultiCore architecture integrating look-up tables (LUTs), product-term logic, and embedded system blocks (ESBs) for on-chip memory, making it a System-on-a-Programmable-Chip (SOPC) platform. FPGAs sit hierarchically under programmable logic devices (PLD), alongside CPLDs, and above standard logic ICs in the semiconductor taxonomy. Key features of the EP20K400FC672-2 include 1664 Macrocells, 502 maximum user I/O, 2.5 ns pin-to-pin propagation delay (-2 speed grade), embedded SRAM organized via ESBs, MultiVolt I/O supporting multiple interface standards, and a 672-pin FC-FBGA package suitable for high-density surface-mount designs. The device supports in-system programming via the IEEE 1149.1 JTAG interface and is configured from a serial PROM or system memory. The APEX-20K architecture combines four types of logic resources—LUTs for register-intensive functions, product-term logic for wide combinational paths, ESBs for memory and arithmetic, and a high-bandwidth interconnect fabric. With 0.22 µm CMOS technology and 2.5 V core, the EP20K400FC672-2 achieves a balance of density and power efficiency for telecom, networking, and DSP applications. Typical applications include telecommunications infrastructure, high-speed data switching, DSP co-processing, prototyping ASICs, and industrial control systems. The 672-ball BGA package supports high-speed signal integrity required by parallel bus interfaces and LVDS links. When designing with this device, ensure proper decoupling with 0.1 µF and 0.01 µF capacitors near each power pin. Configuration storage via EPC2 or EPC16 serial configuration devices is recommended for production. The device is now in EOL/NRND status—designers of new systems should consider Cyclone or Stratix families. This page synthesizes distributor stock, FPGA family cross-references within the APEX-20K portfolio, and design notes not consolidated in the original Altera datasheet.
EP20K400FC672-3 - APEX 20K 400K FPGA, 672-FBGA | Altera
The Altera (Intel Programmable Solutions Group) EP20K400FC672-3 is a member of the APEX 20K family of FPGAs (Field-Programmable Gate Arrays) implementing 400,000 system gates over 16,640 logic elements (cells) with MultiCore architecture. The device is housed in a 672-pin fine-pitch BGA (FBGA) package operating at a 2.5 V core supply, with 502 user I/O pins and propagation delay figures in the 2.5 ns class, making it a high-density programmable platform for SOPC (System-On-a-Programmable-Chip) integration. The -3 speed grade indicates the commercially fastest silicon bin in this family. An FPGA (Field-Programmable Gate Array) is a type of integrated circuit containing an array of programmable logic blocks, interconnect, and I/O cells that an engineer can configure post-manufacture to implement arbitrary digital functions. Within the taxonomy, the APEX 20K belongs to the high-density SRAM-based FPGA family, sitting between CPLDs (Complex Programmable Logic Devices) at lower density and ASICs (Application-Specific Integrated Circuits) at higher NRE cost. APEX 20K pioneered the MultiCore architecture that integrates lookup-table (LUT) logic, embedded system blocks (ESBs) for memory and specialized functions, and high-speed interconnect into a single fabric supporting SOPC integration, where a soft processor core, peripherals, and custom logic coexist on one die. Key features of the EP20K400FC672-3 include 16,640 logic elements, 502 user I/Os, MultiCore architecture with embedded system blocks, a 672-pin FC-FBGA (Fine-pitch Chip-scale BGA) package for high pin density, 0.22 µm CMOS process technology, 167 MHz internal performance, and a -3 commercial speed grade. The 672-BGA footprint maximizes I/O escape routing for high-bandwidth designs while consuming compact board area compared to equivalent QFP packages. The APEX 20K architecture combines look-up table logic for combinatorial and registered functions with embedded array blocks (EABs/ESBs) that can be configured as RAM, ROM, or specialized arithmetic pipelines. The MultiCore interconnect is segmented to optimize critical-path delays, supporting 167 MHz operation in pipelined datapaths. Designers targeting the EP20K400FC672-3 typically use the Quartus II or MAX+PLUS II toolchain (legacy support) for synthesis, place-and-route, and timing closure. Typical applications for the EP20K400FC672-3 span telecommunications infrastructure (ASIC prototyping, glue logic, high-speed datapath bridging), industrial control and factory automation (custom protocol conversion, real-time control), DSP front-ends (preprocessing, filtering), and legacy computing interfaces (PCI bridges, memory controllers). The 502 user I/Os and 16,640-cell density target medium-complexity system integration where ASIC NRE cost is not justifiable. When designing with this device, verify that the 672-FBGA land pattern and 2.5 V core supply meet your PCB manufacturing and power-delivery budget. Because the APEX 20K family has been in maintenance/legacy status for many years, plan a lifecycle risk-mitigation path: stock a safety inventory, evaluate Cyclone-series successors for new designs, and confirm your compiler toolchain version supports the device. JTAG programming via ByteBlaster or similar download cables is the standard configuration path. This page synthesizes distributor pricing, drop-in same-package alternatives from the APEX 20K family, and practical design notes not found in the manufacturer datasheet, providing a single decision-grade reference for procurement and engineering teams working with the EP20K400FC672-3.
EP20K400FC672-3V - 400K Gates APEX 20K FPGA 672-FBGA | Altera
The Altera (Intel) EP20K400FC672-3V is a member of the APEX 20KC programmable logic device family delivering up to 400,000 system gates with MultiCore architecture that integrates look-up table (LUT) logic, product-term logic, and embedded memory in a single fabric. The device is supplied in a 672-ball FineLine BGA (FC-FBGA, 27x27 mm) and supports an I/O count of 502 pins. Core voltage is 1.71 V to 1.89 V (2.5 V referenced in legacy datasheets for the APEX 20K Vccint rail with separate Vccio banks), and the silicon is fabricated on a 0.22 µm process. Total embedded RAM is 212,992 bits (16640 logic elements / 16,640 cells typical) and the -3 speed grade delivers typical performance up to 167 MHz internal, with a 3.6 ns pin-to-pin delay. An FPGA (Field-Programmable Gate Array) is a programmable logic device containing an array of configurable logic blocks (CLBs), programmable interconnect, and I/O cells that engineers can configure after manufacture to implement arbitrary digital logic. FPGAs sit within the broader semiconductor hierarchy as a sub-category of programmable logic devices (PLDs), themselves part of the logic IC family. The APEX 20K family was one of the first PLDs to combine LUT logic with embedded system blocks (ESBs) that double as dual-port RAM, ROM, or CAM, enabling system-on-a-programmable-chip (SOPC) integration. Key features of the EP20K400FC672-3V include 16,640 logic elements (cells), 212,992 bits of embedded memory, 502 user I/O, MultiCore architecture with embedded system blocks, in-system programmability via IEEE 1149.1 JTAG, and 5 V tolerant I/O with PCI-compliant drivers. The device supports up to 167 MHz internal operation and is suitable for high-density glue-logic, bus-interface, and datapath-replacement designs. Typical applications for the EP20K400FC672-3V include telecommunications line-card controllers, high-speed data-path bridge logic, industrial control backplanes, PCI/PCI-X bus interfaces, and legacy ASIC prototyping. Engineers select this part when a large LUT/embedded-memory fabric is required on a single 5 V tolerant device with proven APEX toolchain support. When designing with this device, observe Vccint decoupling per the APEX 20KC datasheet (DS-APEX20K-5.1): use 0.1 µF and 0.01 µF ceramic capacitors close to every Vccint/Vss pair, and provide a minimum of eight 0.2 µF bulk capacitors around the package perimeter. Signal-integrity simulations are recommended above 100 MHz to control simultaneous-switching noise across the 502 I/O. This page synthesizes distributor pricing, drop-in same-package alternatives from the Site MPN list, and practical design notes that are not found on the manufacturer datasheet alone.
EP20K400FC672-3X - APEX 20K 400K Gates FPGA, 672-BGA | Altera
The Altera EP20K400FC672-3X is a high-density APEX 20K family Field-Programmable Gate Array (FPGA) housed in a 672-ball Fine-pitch BGA package (FC-FBGA / FCBGA). Built on a 0.22 µm CMOS process, the device integrates approximately 400,000 gates with 16,640 logic cells and 1664 macrocells, supported by MultiCore architecture that combines look-up table (LUT) logic with embedded memory blocks. It provides 502 user I/O pins (496 dedicated I/O lines per the MicrochipUSA listing) and runs from a 2.5 V core supply with 3.3 V/5 V tolerant I/O banks. The -3X speed grade targets a maximum clock frequency of 181.82 MHz with a typical propagation delay of 2.07 ns, making it suitable for high-throughput datapath and bus-interface designs. An FPGA (Field-Programmable Gate Array) is a semiconductor integrated circuit containing configurable logic blocks (CLBs), programmable interconnect, and I/O cells that the designer can program after manufacture using a hardware description language (HDL). FPGAs occupy the middle ground between fixed-function ASICs and software-driven processors: they deliver hardware-level parallelism and deterministic latency while remaining fully re-programmable. APEX 20K is a system-on-a-programmable-chip (SOPC) family combining look-up-table logic with embedded cache logic (CAM) and dual-port RAM, enabling a single chip to host microcontrollers, datapaths, memory, and high-speed interfaces. Key features of the EP20K400FC672-3X include 16,640 logic elements, 1664 macrocells, MultiCore LUT/CAM architecture, 2.5 V core supply, JTAG/IEEE 1149.1 boundary-scan support, in-system programmability via Altera ByteBlaster or MasterBlaster, and a per-pin I/O slew-rate control. The 672-ball FC-FBGA package supports high-density board layouts with controlled-impedance traces for clock distribution and high-speed LVDS/HSTL signaling. Typical applications include telecommunication line cards, high-speed data-acquisition systems, DSP co-processing front-ends, and industrial control backplanes where parallel logic, large embedded memory, and high I/O count are required. The 502-pin I/O budget comfortably accommodates wide memory buses (e.g., 64-bit SDRAM) alongside multiple standard interfaces such as PCI, UTOPIA, or POS-PHY. The 0.22 µm process offers robust 3.3 V/5 V PCI compatibility that newer sub-100 nm FPGAs have abandoned. Designers should note that the APEX 20K family is mature and approaching end-of-life; long-term availability should be verified against Altera/Intel lifecycle notices before committing to new production designs. The 672-ball BGA requires multilayer PCB fabrication with microvia or via-in-pad technology for reliable assembly and controlled-impedance routing. When migrating to newer families, consider Altera Cyclone III/IV/V or Stratix equivalents, although footprint and core-voltage changes will require PCB re-layout.
EP20K400FC672-4 - APEX 20K FPGA 400K Gates 672-BBGA | Intel
The Intel (formerly Altera) EP20K400FC672-4 is a member of the APEX 20K programmable logic device family, a multi-vendor-architecture (MultiCore) FPGA that integrates look-up table (LUT) logic, embedded system blocks (ESBs) for memory, and I/O elements on a single device. This variant is housed in a 672-ball FineLine BGA (FC) package and is graded for the -4 speed bin (the -4 corresponds to the slowest commercial speed grade in the APEX 20K family, making it suitable for cost-sensitive designs where timing closure is not the primary concern). An FPGA (Field-Programmable Gate Array) is a type of programmable logic device that allows designers to configure digital logic after manufacturing. Within the broader semiconductor taxonomy, FPGAs belong to programmable logic devices -> digital ICs -> integrated circuits. The APEX 20K family pioneered the combination of LUT-based logic and embedded memory in a single fabric, predating the modern Stratix/Cyclone families and serving as a stepping stone to today's heterogeneous SoC FPGAs. The EP20K400FC672-4 delivers up to 400,000 typical gates (roughly 212,992 logic elements per the -1 variant datasheet), 212,992 system gates, 16640 logic elements, and 502 Kbits of embedded memory distributed across the embedded system blocks. Per the verified distributor and datasheet records, the device carries a Moisture Sensitivity Level (MSL) of 3 and a peak reflow rating of 220 C, consistent with surface-mount BGA assembly. Applications for this part span legacy communications infrastructure, industrial control, ASIC prototyping, and glue-logic replacement on legacy boards where the design has been validated against APEX 20K timing models. The 672-pin BGA package supplies abundant user I/O for memory interfaces and parallel bus expansion. Designers working with this part typically rely on the Altera/Intel Quartus II design environment (legacy support). Note that the APEX 20K family has been classified NRND/EOL by Intel in favor of newer Cyclone/Stratix devices, so availability should be verified before starting new designs. The page below combines distributor pricing, equivalent APEX 20K alternatives, and design notes not synthesized in any single manufacturer document.
EP20K400FC784-1 - APEX 20K 400K-Gate FPGA 784-BGA | Altera
The Altera EP20K400FC784-1 is a member of the APEX 20K family of programmable logic devices, integrating 400,000 gates of logic capacity with up to 212 Kbits of embedded memory in a 784-ball PBGA package. It operates from a nominal 2.5 V core supply (2.375 V to 2.625 V range) and supports a maximum clock frequency of 6.1 GHz, making it suitable for high-throughput parallel processing designs. An APEX 20K device is a fine-grained, multi-vendor architecture (MVAA) PLD that combines look-up table (LUT)-based logic, embedded array blocks (EABs) for memory, and a high-bandwidth interconnect. In the broader taxonomy, the APEX 20K is a high-density FPGA positioned between the older FLEX 10K and the later Stratix families, optimized for data-path and DSP-style functions on a single programmable die. Key features include 212 Kbits of embedded SRAM, four dedicated clock inputs, multiVolt I/O supporting 1.8 V/2.5 V/3.3 V interfaces, JTAG boundary-scan test, and an embedded PLL for clock multiplication and skew management. The device supports in-system configuration via serial or parallel configuration modes using Altera MAX+PLUS II or Quartus design tools. The APEX 20K architecture combines four-input LUTs grouped into Logic Array Blocks (LABs) with EABs that can implement dual-port RAM, ROM, FIFOs, and multiplier functions. This heterogeneous fabric, the first of its kind in the industry when introduced, allows efficient implementation of both control logic and data-path arithmetic on the same device. Designers can allocate logic and memory density independently to optimize silicon utilization. Typical applications include telecommunications line-card processing, ASIC prototyping, high-speed data acquisition front-ends, and DSP co-processing. The combination of high logic density, embedded memory, and flexible I/O made the APEX 20K family a popular platform for telecom infrastructure and test equipment in the early 2000s. When designing with this device, allocate configuration pins carefully: dedicated configuration, JTAG, and clock pins have fixed locations and cannot be repurposed. The 784-ball PBGA package requires a 1.27 mm ball pitch PCB layout with controlled-impedance routing for high-speed I/O. Always consult the APEX 20K datasheet before designing the power decoupling network, as the device has multiple VCC rails (core, I/O banks, PLL). This page synthesizes Altera APEX 20K family specifications, alternative sourcing options, and PCB layout guidance not found in the original manufacturer datasheet. Engineers seeking an EP20K400FC784-1 replacement should review the alternatives section, which lists same-package APEX 20K variants with identical ball maps.