FPGA & CPLD
Produits (6666)
EP610SC-20 - 16-Macrocell Classic EPLD, 22ns, 5V, SOIC-24
The Altera (Rochester Electronics) EP610SC-20 is a 16-macrocell Classic-family Erasable Programmable Logic Device (EPLD) delivering pipelined data rates up to 100 MHz with a 22 ns propagation delay, housed in a 24-pin plastic small-outline (SOIC-24 / PDSO24) package. Originally an Altera-classic part, the EP610SC-20 is now manufactured/re-distributed by Rochester Electronics as an authorized source for legacy EPLD demand, with active lifecycle status and 300 gate equivalents at 5V CMOS operation. An EPLD (Erasable Programmable Logic Device) is a non-volatile reprogrammable logic device that sits in the programmable logic hierarchy between simple PAL/GAL devices and modern CPLDs/FPGAs. Classic EPLDs use EPROM cells to store the configuration, providing true non-volatile instant-on behavior without external boot memory. The EP610 family belongs to Altera's first-generation classic architecture, later succeeded by MAX-series CPLDs, and is often specified for long-lifecycle industrial, telecom, and aerospace systems where modern FPGAs are unacceptable for legacy reasons or where instant-on logic glue is required. Key features of the EP610SC-20 include 16 macrocells (24-pin logic capacity), 22 ns tPD combinational delay enabling 100 MHz pipelined operation, 5V CMOS I/O, and 300 gate equivalent density. The 24-pin SOIC package offers easy through-hole-compatible SMT assembly and supports JTAG-free ISP via Altera's classic programming algorithm using dedicated programming pins. Power consumption is moderate for the 5V CMOS process, and the device is specified over commercial and industrial temperature grades depending on sub-variant. The EP610SC-20 uses Altera's classic EPLD architecture with EPROM-configured AND/OR arrays feeding 16 flip-flop-equipped macrocells. Each macrocell offers configurable D/T/JK flip-flop polarity, feedback paths, and output enable control. With 22 ns tPD and registered throughput up to 100 MHz, the architecture targets glue-logic, address decoding, state-machine, and bus-interface applications that benefit from instant-on non-volatile configuration. The CMOS EPROM cell provides bit-level reprogrammability with UV-windowed ceramic variants historically available for engineering development. Typical applications include legacy industrial control board replacement, telecom infrastructure glue logic, address decoding and bus arbitration in 5V embedded designs, 5V state machines, and military/aerospace sustainment programs that require drop-in Altera-classic form-fit-function continuity. Rochester Electronics' ongoing manufacture makes the EP610SC-20 a viable long-term sustainment part. When designing with this device, ensure your design fits within the 16 macrocell and ~300 gate-equivalent logic capacity, as overflow requires logic partitioning across multiple devices. Verify the 5V VCC tolerance of downstream logic since 5V CMOS outputs may exceed 3.3V tolerance of newer devices. This page synthesizes distributor pricing, Rochester Electronics lifecycle status, drop-in EPLD alternatives, and practical design notes not found in the original Altera datasheet alone.
EP9100C-30 - 900 Gates Classic EPLD, 30ns CMOS | Intel / Altera
The Intel / Altera EP9100C-30 is a member of the Altera Classic EPLD (Erasable Programmable Logic Device) family, fabricated on advanced CMOS technology and offered in a commercial 30 ns pin-to-pin propagation delay speed grade. The EP9100C-30 integrates approximately 900 usable gates of programmable logic with 48 macrocells and 24 flip-flops, packaged in a 40-pin ceramic DIP (J-Lead CDIP option also available) footprint commonly seen in legacy Altera Classic EPLDs. The Classic family provides high-speed, low-power logic integration for glue-logic, decoder, state-machine, and bus-interface applications that predate modern CPLD/FPGA architectures. A Classic EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL-style macrocell arrays on a single CMOS die, erasable via ultraviolet light (windowed packages) or one-time-programmable (OTP) in ceramic DIP form. In the broader taxonomy, EPLDs sit below CPLDs (Complex PLDs) and FPGAs (Field-Programmable Gate Arrays); they are predecessors to today's MAX II/MAX V CPLD families from Intel (formerly Altera). EPLDs offer deterministic pin-to-pin timing, predictable interconnect delays, and instant-on operation because the configuration is stored in non-volatile memory rather than loaded from an external flash at boot. Key features of the EP9100C-30 include a 30 ns combinatorial propagation delay (tPD), a maximum toggle frequency of 62.5 MHz (from the -30 speed grade), 48 macrocells with 24 flip-flops, 24 dedicated input pins, and I/O organized around a Programmable Interconnect Array (PIA). The device supports 5 V single-supply operation (VCC = 4.75 V to 5.25 V), TTL-compatible inputs and outputs, and offers three speed grades (-20, -25, -30, -35) plus a military / MIL-STD-883 variant (EP9100C-30/883). Programming is performed via the Altera Altera Programming Unit (APU) or compatible third-party programmers using the JEDEC fuse-map format. The EP9100 architecture uses a sum-of-products (AND-OR) macrocell fed by a global Programmable Interconnect Array. Each macrocell contains a programmable AND array, a fixed OR array, an output flip-flop with programmable clock/clear/preset controls, and an I/O pin with tri-state control. Compared to PAL/GAL devices, the EP9100 adds the PIA, which routes any input or feedback signal to any macrocell - enabling true sum-of-products logic for any function. Compared to modern MAX V CPLDs, the EP9100C-30 has lower logic density and slower speeds, but its instant-on non-volatile architecture and 30-year production heritage make it a reliable choice for legacy equipment sustainment and aerospace/defense systems where re-design qualification is costly. Typical applications include legacy industrial controller glue logic, address decoding for 8086/68000 microprocessor systems, state-machine replacement of discrete 74LS logic, TTL-to-CMOS bus bridging, and aerospace/defense equipment with established reliability data. The EP9100C-30 is also widely used as a drop-in replacement for discrete SSI/MSI logic clusters in 5 V designs where power, board area, and reliability improvements are needed. When designing with the EP9100C-30, ensure the input rise/fall times are faster than 100 ns to prevent additional propagation delay, and derate outputs according to the DC output current vs. VCCOL curves in the datasheet. Use a bypass capacitor of at least 0.1 µF close to each VCC pin to suppress switching transients on the global PIA clock network. For new designs, consider the Intel MAX V CPLD family (e.g., 5M80ZE64) as a modern equivalent with more density and lower power; however, the EP9100C-30 remains preferred for legacy 5 V systems with established firmware/silicon qualification. This page synthesizes distributor availability, JEDEC-spec parametric comparison data, and practical design notes not consolidated in the original Altera Classic EPLD datasheet.
EP910DC-15 - Classic EPLD 900 Gates 15ns DIP-24 | Altera
The Altera EP910DC-15 is a member of the Classic EPLD (Erasable Programmable Logic Device) family, providing high-speed, low-power CMOS logic integration in a 24-pin ceramic DIP (DC) package. The device is speed grade 15, indicating a 15 ns maximum pin-to-pin propagation delay, and is specified for the commercial operating temperature range. Built on advanced CMOS EPROM technology, the EP910 delivers approximately 900 usable gates of combinatorial and registered logic for glue-logic, bus decoding, state-machine, and address- decoding applications that previously required multiple discrete TTL or CMOS SSI/MSI parts. An EPLD (Erasable Programmable Logic Device) is a one-time- or UV-erasable non-volatile programmable logic IC from the late-1980s/early-1990s era, sitting in the device hierarchy between simple PAL/GAL SPLDs and modern SRAM-based FPGAs. EPLDs integrate multiple AND/OR arrays, programmable macrocells, and a fixed interconnect into a single package, giving designers higher density and predictable timing compared to discrete 22V10-style PALs while remaining simpler and cheaper than contemporary FPGAs. Altera's Classic family extended this concept by sharing a uniform macrocell architecture across EP310, EP320, EP610, EP910, EP1800 and EP1810 densities, allowing seamless design migration through the same toolchain. Key features of the EP910DC-15 include 24 macrocells, 12 dedicated inputs, 12 bidirectional I/O pins, 10 flip-flops, 24 product terms per macrocell, and a 15 ns tPD. The device is erasable via a quartz window (ceramic DIP package only), enabling prototype iteration and field re-programming on the same silicon. I/O structures are TTL-compatible and the part supports either 5V-only or, on later die revisions, 5V/3.3V mixed-voltage operation, making it suitable for bridging legacy and modern logic rails in brownfield designs. A logic-lock feed-through path and pin-keeper circuits reduce external glue requirements. Architecturally, the EP910 implements a sum-of-products PLA structure feeding a flexible output macrocell. Each macrocell contains a programmable flip-flop, output enable, and feedback path that can be reconfigured post-fit to implement D/T/JK flip-flops, latches, or pure combinatorial output with selectable polarity. This uniform architecture yields predictable, deterministic timing - a key reason Classic EPLDs were preferred over early SRAM-based FPGAs for control logic where tCO and tSU needed to be fixed at compile time. Power consumption is approximately 200-400 mW active at 25 MHz, depending on utilization and toggle rate, and drops to a low CMOS standby in idle. Typical applications include address decoding and chip-select generation in 8086/68k/MIPS-based microprocessor systems, bus arbitration, DRAM/VRAM control logic, channelized interface glue between legacy peripherals, firmware state machines for disk controllers, and industrial PLC ladder-logic replacement. The 24-pin DIP form factor is also convenient for through-hole prototype boards, educational labs, and legacy equipment repair where surface-mount adapters would be impractical. When designing with the EP910DC-15, treat the 15 ns tPD as a hard budget: derive fMAX from the registered tCO + logic + tSU path and de-rate by 20% for setup margin. Decouple VCC with a 0.1 uF ceramic plus 10 uF tantalum placed within 5 mm of the pins, and reserve the unused macrocells as outputs driving a known state to avoid bus contention during ISP. For new designs, prefer Altera MAX II or Lattice ispMACH 4000 families; the EP910DC-15 is recommended only when matching an existing pinout or repairing installed equipment. This page synthesizes distributor pricing snapshots, same-brand and cross-brand drop-in alternatives, and practical design notes not assembled on any single manufacturer or distributor datasheet.
EP910DC-30 - 900-Gate UV EPLD, 24 Macrocells, DIP-40 | Altera / Intel
The Altera / Intel EP910DC-30 is a 900-gate CMOS UV-erasable / OTP Erasable Programmable Logic Device (EPLD) from the Classic EPLD family, packaged in a 40-pin ceramic or plastic DIP and rated for 30 ns pin-to-pin propagation delay (the "-30" speed grade). The part delivers 24 macrocells interconnected through a global programmable interconnect, supports two external clock inputs, and offers 36 dedicated input pins plus 24 output macrocells for I/O. It is the largest member of the EP910 family and is typically used as a glue-logic replacement for multiple 22V10-style PALs. What is an EPLD? An EPLD (Erasable Programmable Logic Device) is a member of the Programmable Logic Device (PLD) family that sits in the taxonomy between simple PAL/GAL (Programmable Array Logic / Generic Array Logic) and full FPGAs. EPLDs use a sum-of-products AND-OR architecture with a fixed OR array, providing deterministic, glitch-free combinatorial and registered logic at modest gate counts (100 to a few thousand gates). EPLDs hold a special role in the modern logic-device hierarchy: PLD -> EPLD -> CPLD -> FPGA, where EPLDs and CPLDs are favored for fast pin-to-pin timing, predictable I/O behavior, and instant-on power-up with no external configuration memory. The EP910's classic AND-OR plane makes it well suited to state machines, address decoding, and interrupt control logic where timing predictability matters more than raw density. Key features of the EP910DC-30 include 33.3 MHz maximum flip-flop toggle frequency, 30 ns tPD / 25 ns tCO combinational timing, 24 macrocells with configurable D/T/JK flip-flops, individually programmable output macrocells with tri-state control, and CMOS low-power operation with 5 V supply. The UV-erasable windowed package permits laboratory prototyping and design iteration, while the OTP variant supports production programming. The EP910 architecture uses Altera's second-generation Classic EPLD macrocell, which combines a programmable product-term array feeding a configurable flip-flop and output cell. Logic is implemented as sum-of-products equations compiled by Altera's MAX+PLUS II or later Quartus tools (legacy Classic device support), with JEDEC fuse-map programming. Outputs support four user-selectable configurations (registered, combinatorial, tri-state, open-drain options per macrocell). Typical applications include PDP-11 / VMEbus / Multibus address decoding, 24/32-bit microprocessor glue logic replacement of 74LS/74F logic, peripheral controller state machines, asynchronous bus interface adapters, and legacy industrial control retrofits where timing-deterministic logic outperforms SRAM-based FPGAs. When designing with the EP910DC-30, remember that the DIP-40 footprint imposes a fixed 600-mil row spacing; allocate board area accordingly, and route the two dedicated clock pins (CLK1/CLK2) with controlled impedance if used at the 33.3 MHz toggle rate. Outputs are 5V TTL-compatible but the inputs tolerate TTL thresholds; no 3.3V tolerance exists, so use a level translator when interfacing to modern 3.3V logic. This page synthesizes distributor pricing, drop-in same-package alternatives from the EP910/EP610 family, and practical design notes not found on a single distributor listing.
EP910DC-35 - 35ns 900-Gate CMOS UV PLD DIP-40 | Intel / Altera
The Intel / Altera EP910DC-35 is a 35ns propagation-delay UV-erasable CMOS Programmable Logic Device (PLD) from the Classic EPLD EP910 family, packaged in a 40-pin ceramic DIP (CDIP-40) with through-hole leads. It delivers 900 usable gates, 24 macrocells, 36 inputs (12 dedicated + 24 I/O lines) and 24 outputs, with 240 product terms available for sum-of-products logic implementation at a maximum clock frequency of approximately 37 MHz. The device operates from a single 5V supply (4.75V to 5.25V) over the commercial 0°C to 70°C temperature range. A Programmable Logic Device (PLD) is a digital integrated circuit whose internal AND/OR array and output macrocell logic can be configured by the user to implement arbitrary combinational and registered Boolean functions, replacing discrete SSI/MSI gate packages. PLDs sit beneath FPGAs in the programmable-logic hierarchy and are subdivided into PAL-type (one-time programmable or UV-erasable), GAL/EPLD (electrically erasable CMOS) and CPLD (complex PLD, multiple macrocell blocks with central interconnect) families. The EP910 sits at the high end of the Classic EPLD family, providing register-intensive glue-logic integration for bus interface, address decoding and state-machine consolidation. Key features of the EP910DC-35 include 35ns pin-to-pin propagation delay (the slowest speed grade of the EP910DC series), 24 flip-flop-equipped macrocells, JEDEC-standard fuse-map programming, a UV-erasable quartz window on the ceramic package for development iteration, and TTL-compatible I/O. Architecturally the EP910 uses a sum-of-products AND-OR array feeding a flexible macrocell block that can be configured as D, T, JK or SR flip-flop, or as combinational output with selectable polarity. The device is specified at 5V ±5% with 5.25V absolute maximum. Typical applications include TTL/CMOS logic consolidation on VMEbus and Multibus adapter cards, address decoding for 8086/68000/80386 microcomputer boards, peripheral controllers (DMA, interrupt, wait-state generation), industrial state machines, and replacement of legacy 24-pin PAL glue-logic clusters. The ceramic DIP-40 windowed package makes the part especially suitable for prototype and low-volume production where in-house UV erase and reprogram cycles are practical. Design consideration: the ceramic DIP-40 quartz-windowed package requires a UV eraser for reprogramming (typically 20-30 minutes of 12,000 µW/cm² short-wave UV). Production users should migrate to the OTP plastic DIP variant (EP910PC-35) once logic is frozen, or to the pin-compatible but electrically erasable 5ns MAX-class CPLD family when higher density is required. This page synthesizes distributor stock and pricing, drop-in EP910 speed-grade alternatives from the same Classic EPLD family, and practical design notes that are not assembled in any single manufacturer datasheet, helping engineers source or substitute this legacy part with confidence.
EP910DC-40 - 24-Macrocell UV EPLD, 25 MHz, DIP-40 | Altera
The Altera EP910DC-40 is a UV-erasable, 24-macrocell Erasable Programmable Logic Device (EPLD) from the Classic EP910 series, supplied in a 40-pin ceramic DIP package and rated for 40 ns propagation delay with up to 25 MHz maximum operating frequency. It integrates 24 macrocells interconnected through a global programmable interconnect, with 12 dedicated inputs and 24 bidirectional I/O pins delivering a combined 36 inputs to the logic array. An EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic device that fuses the architectural simplicity of PAL-type logic with the re-programmability of UV-erasable EPROM cells. Within the broader taxonomy, EPLDs sit between simple SPLDs (such as PALs and GALs) and modern FPGAs, offering deterministic combinational and registered logic, predictable timing, and erasable programmability at the cost of lower density than an FPGA. The EP910 family belongs to the Classic EPLD category introduced by Altera in the 1980s and remains in service today for legacy industrial and military refresh designs. Key features of the EP910DC-40 include a maximum propagation delay of 40 ns (commercially graded; the -40 suffix indicates 40 ns tPD), an internal global interconnect that links all 24 macrocells through a single unified bus, up to 240 product terms distributed across the array, two dedicated global clock inputs for synchronous sequential logic, and on-board logic test circuitry enabling AC specification verification during standard production flow. The part is built on a CMOS process that consumes modest power compared with bipolar PAL alternatives of the same era. Architecturally, the EP910DC-40 uses a PAL-type AND/OR structure in each macrocell. Combinational logic is implemented via AND-plane product terms feeding an OR gate that drives the macrocell output, while registered operation is achieved by routing the OR-plane result through a configurable D flip-flop clocked from one of the two global clock inputs. The 24 I/O pins share connections to both the input array and the macrocell feedback network, allowing pin and feedback resource pooling that maximizes logic utilization per device. Typical applications include legacy glue logic replacement (replacing multiple 24-pin PALs with a single EPLD), bus-interface adaptation (synchronizing 8-bit and 16-bit buses with predictable timing), address decoding for microprocessor and microcontroller systems, industrial control boards that require ceramic-DIP through-hole packages for harsh environments, and military/aerospace refresh programs where the ceramic DIP form factor and Altera Classic EPLD pinout are mandated. Designers should note that the DIP-40 ceramic package has long lead times and a shrinking authorized-distribution channel. Most surviving stock is broker or aftermarket; for new designs engineers typically migrate to Altera MAX II CPLDs or modern Lattice ispMACH CPLDs that provide denser, in-system-programmable, and RoHS-compliant equivalents with similar 5V tolerant I/O characteristics. This page synthesizes distributor pricing, drop-in Classic EPLD alternatives, and practical design notes that are not collated in the original Altera datasheet.
EP910DI-30 - 24-Macrocell EPLD, 30ns, CDIP-40 | Altera (Rochester)
The Altera EP910DI-30 is a UV-erasable Classic EPLD (Erasable Programmable Logic Device) built on a 24-macrocell CMOS array, housed in a 40-pin ceramic DIP (CDIP-40) package and rated for 30 ns pin-to-pin propagation delay. It belongs to the legacy Classic EPLD family that Altera introduced in the late 1980s as one of the industry's first commodity programmable logic products, predating the modern CPLD and FPGA generations. A programmable logic device (PLD) is a general-purpose digital IC whose logic function is set by the end user via on-chip fuses, anti-fuses, EPROM, EEPROM, or SRAM configuration cells. EPLDs sit in the product-type hierarchy: programmable logic device -> erasable PLD -> complex PLD (CPLD) -> semiconductor -> integrated circuit. They were historically used as glue logic, address decoding, state machines, and bus-interface bridges before modern FPGAs and CPLDs took over most of those roles. Key features of the EP910DI-30 include 24 macrocells, 50% of which are user-configurable as registered or combinatorial outputs, 10 dedicated input pins, 12 dedicated I/O pins, and a maximum toggle frequency of 62 MHz. The device operates from a single 5 V supply and is windowed (UV-erasable) for design iteration - it must be removed from the circuit and exposed to UV light to erase. The 30 ns speed grade suits asynchronous state machines, address decoders, and bus-interface logic in legacy 5 V systems. The 40-pin ceramic DIP package is a through-hole form factor with a quartz window on top for erasure, and provides robust thermal and mechanical performance suitable for industrial and military temperature grades. Because the part is supplied through Rochester Electronics (the authorized aftermarket manufacturer for legacy Altera EPLDs), it is targeted at long-lifecycle programs that must keep a 20-30 year production run alive. Typical applications include legacy bus-interface bridging (e.g., 8-bit to 16-bit address demultiplexing), glue logic in industrial controllers, replacement of discrete TTL/MSI logic in avionics and military systems, and state-machine controllers in medical and test equipment where redesign is impractical. Because of the CDIP-40 footprint and 5 V supply, the EP910DI-30 drops directly into boards originally designed for the EP910 family. When designing with this device, engineers should note that modern design tools no longer natively support the EP910 family - programming is typically done with legacy Altera hardware or third-party JEDEC-file programmers. The 5 V supply rail should be well decoupled with 0.1 uF ceramic capacitors adjacent to each VCC/GND pair, and unused inputs must be tied to VCC or GND through a defined logic level rather than left floating. This page synthesizes Rochester Electronics distributor stock data, JEDEC-file programming considerations, and drop-in alternatives for the Classic EPLD family - practical engineering context not found in the original manufacturer datasheet alone.
EP910DI-35 - 24-Macrocell EPLD, 35ns, CDIP-40 | Altera/Rochester
The Altera EP910DI-35 is a Classic EPLD (Erasable Programmable Logic Device) featuring 24 macrocells and 450 usable gates in a 40-pin ceramic DIP (CDIP) through-hole package. The 'DI' suffix denotes the industrial-temperature-range ceramic DIP form factor, and the '35' speed grade indicates a 35 ns propagation delay (tPD). It is an ultraviolet-erasable CMOS PLD from Altera's original Classic EPLD family, manufactured today as a long-life-cycle replacement by Rochester Electronics. The EP910 family sits between the smaller EP900 (16 macrocells) and the larger EP1800 (48 macrocells), filling the popular 24-macrocell mid-density niche for glue-logic, decoder, and bus-interface applications. What is an EPLD? An EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic device that uses EPROM (UV-erasable) or EEPROM technology to store AND/OR logic arrays. EPLDs belong to the broader programmable logic hierarchy: PLD -> CPLD -> FPGA. They provide deterministic pin-to-pin timing, low power consumption, and instant-on behavior with no configuration load step, distinguishing them from SRAM-based FPGAs. Each macrocell combines a programmable AND array feeding an OR term with a configurable flip-flop, providing both combinational and registered outputs. Key features of the EP910DI-35 include 24 macrocells, 10 dedicated input pins, 20 I/O pins (bidirectional), 450 usable gates, a 35 ns maximum pin-to-pin propagation delay, and a 28.6 MHz toggle frequency (fCNT). The device operates from a single 5 V supply (VCC = 4.75 V to 5.25 V) and is fabricated in CMOS technology for low power (Icc typically 40 mA). The CDIP-40 package includes a quartz window on the top of the ceramic body for UV erasure of the EPROM cell array. Architecturally, the EP910 implements a PAL-type AND/OR structure with each macrocell offering a sum-of-products expression plus an optional D flip-flop. Output enable, preset, and clear signals are globally controlled. The 24 macrocells share a common programmable interconnect array optimized for predictable timing, making the part well-suited for state machines, address decoding, and bus arbitration. Typical applications for the EP910DI-35 include bus-interface glue logic in industrial 5 V backplanes, address decoders for microprocessor systems, register/buffer insertion between legacy peripherals, control logic in telecom and military systems requiring ceramic-package reliability, and replacement of multiple 74-series TTL gates. Its industrial -40C to +85C temperature range and ceramic CDIP package make it especially useful where the original Altera die must be sourced through a long-term authorized manufacturer. When designing with the EP910DI-35, note that the device requires a 5 V-only supply (not 3.3 V tolerant on inputs), and that the ceramic DIP footprint is identical to the plastic PDIP-40 EP910PI variant, allowing PCB reuse across temperature grades. Programming requires a standard EPROM/PLD programmer (e.g., Data I/O, BP Microsystems) using a JEDEC fuse map generated by Altera's legacy MAX+PLUS II (or the modern Altera/Intel Quartus Classic support). Erasure requires a UV eraser exposing the window for 20-30 minutes at 12,000 uW/cm2. This page synthesizes distributor pricing, drop-in same-package alternatives from the Site MPN list, and practical design notes not consolidated in any single distributor listing.
EP910DM-40 - 24-Macrocell UV EPLD Classic PAL-Type | Altera
The Altera EP910DM-40 is a UV-erasable programmable logic device (EPLD) from the Altera Classic EP910 family, fabricated on advanced CMOS technology and housed in a 40-pin ceramic DIP (Cerdip) package with 40 ns propagation delay. It features 24 macrocells interconnected by a global programmable interconnect bus, 36 dedicated inputs, 24 dedicated outputs, 24 bidirectional I/O lines, and 240 product terms, making it suitable for high-speed, low-power logic integration in glue-logic and state-machine applications. A UV Erasable Programmable Logic Device (EPLD) is a type of programmable logic IC that uses ultraviolet light to erase its configuration before re-programming. EPLDs belong to the broader category of Programmable Logic Devices (PLDs) within the programmable logic semiconductor hierarchy: PLD -> EPLD -> Classic EPLD. The EP910 sits between simpler PAL/GAL devices (typically 8-16 macrocells) and larger CPLDs, providing a balance of logic density and predictable timing. Its PAL-type AND/OR architecture with a global bus provides deterministic pin-to-pin delays, which is why EPLDs remained popular for asynchronous state machines and bus-interface glue logic long after FPGAs became mainstream. Key features include 24 macrocells with user-configurable I/O, a non-volatile UV-erasable configuration memory, 4 dedicated clock inputs supporting two clock domains, and JEDEC-standard fuse-map programming. The EP910DM-40's 40 ns tPD makes it appropriate for control logic running at clock rates up to approximately 20-25 MHz, and its CMOS technology delivers low standby power for always-on systems. Typical applications include address decoding and bus-interface glue logic for microprocessors, asynchronous state machines, custom decoder/replacement logic, and legacy 5V industrial control boards. The DIP-40 ceramic package (windowed Cerdip) allows in-circuit reprogramming via UV erasure, which is valuable for prototyping and field-upgradable equipment. When designing with the EP910DM-40, note that 5V CMOS signal levels are mandatory and that unused I/O pins should be left unconnected or tied per datasheet recommendations. The ceramic DIP-40 (windowed) package retains its UV window for re-erasure, while the plastic OTP variants cannot be re-programmed. This page synthesizes distributor availability, parametric datasheet figures, and Altera EP910 cross-family variant listings that go beyond the standalone EP910 datasheet, helping engineers source and substitute this legacy Classic EPLD part.
EP910DM/883B - Altera Classic EPLD, 24 Macrocells, MIL-883B | Intel / Altera
The Intel / Altera EP910DM/883B is a member of the Altera Classic EPLD family that delivers high-speed, low-power CMOS logic integration in a 24-pin ceramic DIP (Cerdip) package. Fabricated on an advanced CMOS process, this part provides 24 macrocells, 10 dedicated input pins, 12 I/O pins, and a maximum propagation delay on the order of nanoseconds, making it suitable for glue-logic, bus decoding, and state-machine replacement in long-life-cycle military and aerospace programs. Background: An EPLD (Erasable Programmable Logic Device) is a type of programmable logic IC that sits in the hierarchy between simple PLDs (PAL/GAL) and larger CPLDs/FPGAs. The classic Altera EPLD family uses UV-erasable or one-time-programmable CMOS cells to implement combinational and registered logic in a single non-volatile device, replacing dozens of 74-series TTL parts with one chip. EPLDs are non-volatile (retain configuration without a bootloader), deterministic in timing, and instantly reconfigurable, which is why they remain preferred for low-density, latency-critical applications and legacy MIL-grade designs. Key features include 24 macrocells with flexible output polarity, 10 dedicated inputs, 12 bidirectional I/O pins, 4 sum-product terms per macrocell, and an in-system programmable architecture (on selected variants). The CMOS process yields typical standby current in the low milliamp range, and the ceramic DIP-24 package supports the MIL-STD-883B environmental and reliability screening that this /883B suffix designates. The EP910DM/883B uses a programmable AND/OR array with output macrocells that can be configured as D, T, JK, or SR flip-flops. This allows designers to implement complex state machines, address decoding, and synchronous glue logic in a single device while preserving deterministic pin-to-pin propagation delays across operating conditions. Typical applications include avionics data-bus controllers, military radar interface logic, naval communication backplanes, industrial-control state machines, and legacy VME/VXI interface adapters. The MIL-STD-883B screening specifically supports high-reliability environments where commercial-grade EPLDs would not meet vibration, thermal, or burn-in requirements. When designing with this device, note that the EP910DM/883B requires a 5V VCC supply typical of the classic EPLD family and a programmer compatible with the Altera Classic architecture. Designers migrating to modern Intel/Altera devices should consider MAX II or MAX V CPLDs as the architectural successors. This page synthesizes distributor pricing, MIL-grade drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone.
EP910DM883B - 24-Macrocell CMOS EPLD, 40ns, CDIP-40 | Altera
The Altera EP910DM883B is a 24-macrocell Classic-series Erasable Programmable Logic Device (EPLD) fabricated on advanced CMOS technology, offering 36 inputs, 24 outputs, and 240 product terms in a 40-pin ceramic dual in-line (CDIP-40) through-hole package with MIL-STD-883B processing. It is part of the Altera EP910 family of high-speed, low-power PAL-type logic integration devices. What is an EPLD? An EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic device that combines the architectural flexibility of a PLD with erasable (UV-erasable) configuration memory. It sits in the taxonomy: programmable logic -> PLD -> EPLD -> CMOS EPLD. EPLDs were widely used before modern FPGAs and CPLDs became dominant, and remain in service today in legacy industrial, military, and aerospace systems where long-life-cycle, pin-compatible replacements are mandatory. Key features include a typical propagation delay of 40 ns (tPD), a maximum clock frequency of 25 MHz, 24 dedicated macrocells connected via a global interconnect bus, and support for both combinational and registered logic. The PAL-type AND-OR-NOT architecture delivers predictable, deterministic timing. The device operates from a single 5 V supply and is rated across the military temperature range of -55 °C to +125 °C thanks to the /883B MIL-STD screening. The EP910DM883B is housed in a hermetic ceramic DIP-40 (CDIP-40) package that provides exceptional reliability in shock, vibration, and thermal cycling environments. The /883B suffix denotes full MIL-STD-883B Class B processing, including burn-in, temperature cycling, and Hermeticity testing. Typical applications include military and aerospace avionics, industrial control logic glue, legacy interface bridging, and pin-compatible replacement of original Altera Classic EPLDs. The wide temperature range and hermetic package make it ideal for downhole, automotive under-hood, and defense electronics. When designing with this part, engineers should provide a 5 V ±5% supply and route the 40 DIP pins to a 0.1 µF bypass network near the supply pin. UV-erase window programming requires a 12.5 V VPP pulse; for in-system reprogramming, consider a flash-based CPLD as a modern alternative. This page synthesizes distributor pricing, parametric comparison with related EP910/E610 family parts, MIL-STD-883B processing notes, and practical design guidance not found in a single manufacturer PDF.
EP910IDC-15 - 450-Gate, 24-Macrocell Classic EPLD | Altera
The Altera EP910IDC-15 is a 450-gate, 24-macrocell Classic-family Erasable Programmable Logic Device (EPLD) in a 40-pin ceramic DIP (CDIP) through-hole package, with a 15 ns commercial-speed grade. It operates from a single 5 V supply and integrates 24 macrocells, 48 flip-flops, and a programmable AND/OR logic array, providing TTL-compatible glue-logic, decoder, state-machine, and bus-interface functions on a single chip. What is a Classic EPLD? An EPLD (Erasable Programmable Logic Device) is a UV-erasable CMOS programmable logic device that preceded modern CPLDs and FPGAs. The Altera Classic family — of which the EP910 is a member — was among the first commercial products to combine macrocell-based logic with on-chip non-volatile (EPROM) configuration. Architecturally, an EPLD sits in the hierarchy: programmable logic -> EPLD -> Classic EPLD -> PLD -> digital IC. Unlike SRAM-based FPGAs, Classic EPLDs retain configuration when powered off and are erased with a UV eraser, enabling rapid design iteration during development. The EP910 also includes on-board logic test circuitry that allows AC specification verification during production test, a feature uncommon in later CPLD families. Key features of the EP910IDC-15 include a 15 ns pin-to-pin propagation delay (tPD), 66.6 MHz maximum flip-flop toggle frequency (fCNT), 24 macrocells arranged in two logic array blocks, and 10 dedicated input pins plus 24 I/O pins. The device supports programmable security-bit protection and is 100% generically tested in windowed packages. According to the Altera Classic Device Family datasheet, the EP910 series was offered in commercial, industrial, and military temperature grades across DIP, PLCC, JLCC, PGA, and SOIC packages. The EP910 architecture uses a sum-of-products AND/OR logic array feeding 24 macrocells, each with a configurable flip-flop. Logic is implemented by programming EPROM cells that drive the AND array; each macrocell can be configured as D, T, JK, or SR flip-flop, or as combinational output. The internal 5 V CMOS EPROM process yields predictable, glitch-free outputs with TTL-compatible input and output thresholds, making the EP910 easy to interface with legacy 5 V logic families such as 74LS, 74HC, and 74F. Typical applications include 5 V TTL bus decoding, address-mapping glue logic for microprocessor systems, state-machine controllers for industrial equipment, replacement of multiple 74LS/74F PAL/GAL devices, and prototyping logic that will later be migrated to a non-erasable (one-time-programmable) pin-compatible EP910 variant. Designers also used the EP910 in telecom interface cards and military/aerospace systems where windowed ceramic packages were preferred for radiation tolerance and field reprogrammability. When designing with the EP910IDC-15, note that the ceramic DIP package has higher thermal mass than plastic but the same electrical footprint as the EP910PC (plastic DIP) and EP910DC variants. The ID suffix indicates the ceramic DIP form factor, and the C-15 suffix indicates commercial temperature range (0C to +70C) with 15 ns tPD. For new designs, consider modern 5 V-tolerant CPLDs in PLCC or TQFP packages with lower power and faster speeds; the EP910IDC-15 is primarily a legacy support and obsolescence-management part. This page synthesizes distributor pricing, drop-in alternatives from the Altera Classic family, and practical design notes not found in the manufacturer datasheet.
EP910IDI-15 - 24-Macrocell Classic EPLD 15ns | Intel / Altera
The Intel / Altera (formerly Altera Corporation) EP910IDI-15 is a member of the Classic EPLD family, a 450-gate CMOS Complex Programmable Logic Device (CPLD) with 24 macrocells, 36 available I/O pins, and a pin-to-pin propagation delay of 15 ns, housed in a 40-pin Ceramic DIP (CDIP) windowed package. The "I" suffix denotes the industrial temperature grade and the "D" denotes the ceramic CerDIP package with a quartz window for in-circuit reprogrammability via UV erasure, a hallmark of the Classic EPLD family used in development, prototyping, and long-life-cycle industrial systems. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that sits in the programmable-logic hierarchy between simple PAL/GAL devices and high-density FPGAs. The Classic EPLD family, introduced in the late 1980s and still in production via Rochester Electronics for legacy sustainment, is built on a CMOS EPROM-cell architecture and uses the MAX+PLUS II development environment for design entry, fitting, and programming. The EP910 sits in the lower-density end of the Classic family, intended for glue-logic, address decoding, state-machine, and bus-interface tasks that require deterministic 15-ns timing rather than the higher gate counts of FPGAs. Key features include 24 individually programmable macrocells, each configurable as D, T, JK, or SR flip-flop or for combinatorial operation; 36 user I/O pins on the 40-pin CerDIP; a 15 ns pin-to-pin logic delay supporting counter frequencies up to approximately 66.6 MHz; and on-board logic-test circuitry that allows AC specification verification during production flow. The device is programmed using the Altera Logic Programmer card and the MAX+PLUS II software suite. All Classic EPLD members are pin-, function-, and programming-file compatible across speed grades and package variants, simplifying design migration. Typical applications include address decoding and glue logic in legacy 5V microprocessor systems, bus-interface adapters for ISA/VME/Motorola bus architectures, replacement of multiple discrete PAL/GAL devices, industrial control state machines, and military/aerospace systems requiring ceramic-packaged, windowed reprogrammable logic for field updates. The CDIP-40 ceramic package with UV window supports field erasure and reprogramming, which is critical for long-life-cycle defense and aerospace sustainment programs. When designing with the EP910IDI-15, note that this part operates from a single 5V supply and is fully static - there is no minimum clock frequency. Designers migrating from plastic DIP or PLCC EP910 variants (EP910PC-25, EP910LC-15, etc.) can drop in the same pinout but should account for the ceramic package's thermal characteristics if used in sealed or high-temperature environments.
EP910ILC-12 - 24-Macrocell 12ns Classic EPLD | Intel / Altera
The Intel / Altera EP910ILC-12 is a 24-macrocell Classic EPLD (Erasable Programmable Logic Device) from the Altera EP910 family, housed in a 28-pin PLCC (J-Lead) package with a 12 ns maximum propagation delay. It operates from a single 5 V supply (4.75 V to 5.25 V) and integrates 24 macrocells with 16 dedicated feedback paths to support combinational and registered logic up to approximately 450 usable gates. A Classic EPLD (Erasable Programmable Logic Device) is an early-generation programmable logic device using UV-erasable CMOS architecture. EPLDs sit in the programmable logic hierarchy above discrete SSI/MSI gates but below modern CPLDs and FPGAs in density. They belong to the broader category of programmable logic ICs, sitting between PALs (Programmable Array Logic) and contemporary CPLD/FPGA devices. Each macrocell contains a programmable AND/OR array and a configurable flip-flop, allowing the chip to replace multiple discrete 74-series logic ICs on a board. Key features include a 12 ns pin-to-pin propagation delay (tPD), 24 macrocells with 16 dedicated feedback paths, a 5 V ±5% supply range, and a JEDEC-standard 28-pin PLCC J-lead surface-mount package. The device is non-volatile - the logic configuration is stored in UV-erasable EPROM cells, providing instant-on behavior at power-up with no external boot memory required. The EP910 family is one of the longest-running Altera Classic EPLD families and is widely recognized for deterministic timing. The EP910ILC-12 uses a CMOS EPROM-cell AND/OR plane feeding 24 output macrocells, each with a configurable flip-flop, output enable, and product-term steering. Programming is performed via a standard Altera programming algorithm using a master/slave serial or parallel mode. Because the configuration is non-volatile, there is no boot sequence, JTAG configuration, or bitstream loading - the part begins executing its logic immediately after VCC is stable. Typical applications include glue-logic replacement in legacy 5 V systems, address decoding and bus-interface logic, state machines for industrial control boards, and prototyping replacements for discrete 74LS/74HC logic. The 12 ns tPD suits bus cycle times down to roughly 33 MHz, making it usable as a peripheral decoder in 8-bit and 16-bit microcontroller or 80x86 designs. When designing with this device, note that the 'I' suffix indicates the industrial temperature grade (-40 °C to +85 °C) and the 'C' suffix indicates the PLCC J-Lead package. Programming requires a UV windowed ceramic device variant (not provided in the PLCC J-lead 'C' suffix used here) or a one-time-programmed plastic package. Verify programming toolchain and software version compatibility with the specific lot date code. This page synthesizes distributor pricing, a drop-in replacement shortlist, and practical design notes not found in any single manufacturer datasheet, optimized for engineers sourcing legacy Classic EPLDs.
EP910ILC-15 - 24 Macrocells, 66.6MHz CPLD | Altera Classic Family
The Altera (Intel) EP910ILC-15 is a member of the Classic EPLD (Erasable Programmable Logic Device) family, providing 450 gates and 24 macrocells in a 44-pin PLCC package with a 15ns propagation delay. It operates from a single 5V supply and is rated for industrial temperature ranges, supporting through-hole surface-mount assembly. The EP910ILC-15 is fabricated using EPROM (UV-erasable) technology, enabling in-system prototyping with subsequent erasure and reprogramming cycles. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that combines the architecture flexibility of a PLD with the density of a small FPGA. In the system-on-chip hierarchy, a CPLD sits between discrete 74-series logic gates and an FPGA, offering deterministic timing, instant-on behavior, and pin-to-pin compatibility across logic density variants. The EP910 family belongs to the legacy Classic EPLD line that pre-dates the modern MAX series and is now maintained by Rochester Electronics as a long-life product. Key features of the EP910ILC-15 include 24 macrocells, 36 user I/O pins, 15 ns pin-to-pin propagation delay (tPD), a maximum internal operating frequency of approximately 83.33 MHz, and zero standby power. The device integrates an on-chip programmable interconnect, a JTAG-compatible test interface for in-system verification, and supports 5V CMOS or TTL input/output levels. The EPROM cell technology provides non-volatile configuration that retains state through power cycles without an external boot PROM. Architecture-wise, the EP910 family is built on a CMOS EPROM process with a sum-of-products logic structure feeding into a fixed OR array. Each macrocell contains a programmable flip-flop, output enable, and feedback path. The device supports logic synthesis through the MAX+PLUS II development environment (legacy tool flow), and parts can be re-programmed by exposing the package window to UV light for approximately 20 minutes followed by re-loading of the JEDEC fuse map. Typical applications of the EP910ILC-15 include glue-logic replacement for 74LS/74HC discrete gates, address decoding in legacy 8-bit and 16-bit microprocessor systems, bus interfacing between asynchronous peripherals and main processors, state-machine control of electromechanical subsystems, and prototyping platforms for verification of synchronous logic prior to ASIC tape-out. When designing with this part, remember that the PLCC-44 package requires a through-hole socket or careful reflow profile, and that the 15ns grade targets 66.6MHz system clocks rather than high-speed DSP pipelines. For new designs, verify whether the contemporary MAX V or MAX 10 CPLD families can deliver equivalent logic density at lower standby current. This page synthesizes Rochester Electronics authorized stocking information, Altera datasheet parametric excerpts, and practical drop-in alternatives not found in the original manufacturer datasheet - enabling faster procurement decisions for long-life-cycle industrial programs.
EP910ILC-15N - 450 Gate 24-Macrocell Classic CPLD, 15ns, 5V, 44-PLCC | Altera
The Altera EP910ILC-15N is a 450-gate, 24-macrocell Classic-family CMOS Complex Programmable Logic Device (CPLD) housed in a 44-pin Plastic Leaded Chip Carrier (PLCC) package. Operating from a single 5 V supply with 15 ns maximum pin-to-pin propagation delay, it delivers up to 66.6 MHz system clock performance in a through-hole-compatible, surface-mountable J-lead package. A CPLD (Complex Programmable Logic Device) is a non-volatile, instant-on programmable logic device that sits between simple SPLDs/GALs and higher-density FPGAs in the programmable logic hierarchy. CPLDs use a classic AND/OR plane architecture with a deterministic interconnect, EEPROM or EPROM configuration memory, and predictable timing that is independent of routing path. They are typically chosen over FPGAs when designs require fast input-to-output response, simple glue-logic integration, power-on instant-on behaviour without an external boot PROM, and I/O-rich, low-density logic capacity. The Classic family from Altera was an early-generation architecture that combined low static power with simple development tools such as the MAX+PLUS II environment. Key features of the EP910ILC-15N include 24 macrocells partitioned into logic blocks, 36 user I/O pins, 16 dedicated input pins, JTAG-compliant IEEE 1149.1 boundary-scan test support, and programmable output slew-rate control. The 15 ns speed grade enables combinational logic at moderate clock rates suitable for bus-interface, address-decoding, and peripheral-control tasks. Internally, the device uses a sum-of-products architecture with each macrocell containing a flip-flop and programmable output polarity. The 5 V CMOS I/O structure is TTL-compatible on inputs and capable of sinking 12 mA per output, allowing direct interface with 74-series logic, microprocessors, and SRAM without external buffers. The PLCC-44 package offers socketability for prototyping and field upgrades. Typical applications include legacy ISA/PCI bus interface logic, address decoding and glue logic for 8051/Microprocessor systems, state-machine controllers, and peripheral bus arbiter replacement. The instant-on non-volatile configuration makes the EP910ILC-15N particularly attractive in industrial-control and military-aerospace designs where boot-time predictability is essential. When designing with this part, observe the 5 V VCC tolerance and provide adequate decoupling (0.1 uF per supply pin plus a bulk 10 uF tantalum). For high-speed designs, respect the 15 ns tPD timing budget and use the JTAG port for in-system programming. This page synthesises distributor pricing from Rochester Electronics and other sources, drop-in alternative MPNs, and practical design notes not consolidated in the original manufacturer datasheet.
EP910ILC-25 - Classic EPLD, 24 Macrocells, 25ns | Intel (Altera)
The Intel (formerly Altera) EP910ILC-25 is a classic Erasable Programmable Logic Device (EPLD) from the EP910 family, offering 24 macrocells, 36 user I/O pins, and a 25 ns propagation delay in a 44-pin JLCC windowed ceramic package suitable for engineering development and reprogrammable prototyping. An EPLD (Erasable Programmable Logic Device) is a type of programmable logic that combines the non-volatility and re-programmability of EPROM technology with the combinatorial and registered logic density needed to replace multiple discrete TTL/CMOS glue-logic devices. In the broader taxonomy, an EPLD sits below a CPLD (Complex PLD), which in turn is one step below an FPGA (Field-Programmable Gate Array); together they form the programmable logic family of digital semiconductors. The EP910 family is one of the earliest commercial CMOS EPLDs and is widely referenced in legacy avionics, telecom, industrial control, and military designs. Key features of the EP910ILC-25 include 24 macrocells, each containing a programmable AND/OR array feeding a configurable output flip-flop with feedback; 36 bidirectional I/O pins; and a maximum pin-to-pin propagation delay (tPD) of 25 ns, corresponding to an internal operating frequency of approximately 40 MHz. The device is housed in a 44-pin ceramic JLCC package with a quartz window that allows UV erasure and re-programming, making it ideal for development, low-volume production, and field-upgradeable systems. Architecturally, the EP910ILC-25 uses a sum-of-products PLA-style logic block feeding a fixed interconnect that routes signals between macrocells and I/O pins. Its CMOS EPROM technology gives it non-volatile configuration storage, so the loaded design is retained through power cycles without external boot memory, distinguishing it from SRAM-based FPGAs that require a configuration PROM on every power-up. Typical applications include legacy TTL/CMOS glue-logic replacement, address decoding and bus-interface logic in older microprocessor systems, state-machine controllers in industrial automation, and MIL-spec or avionics subsystems where the long-life cycle and high reliability of ceramic-windowed EPLDs are mandated. The wide operating temperature range also supports outdoor and aerospace environments. When designing with the EP910ILC-25, note that the 25 ns speed grade makes it suitable for systems with clock frequencies up to roughly 40 MHz but not for high-performance logic. Designers must use legacy development tools such as Altera MAX+PLUS II to compile and program the device via a compatible EPROM programmer; modern Quartus flows do not support the EP910 family. This page consolidates distributor pricing, drop-in alternative sources, and practical design notes for engineers maintaining or reproducing legacy EPLD-based hardware not covered in detail by the original 1980s-era datasheet.
EP910ILC-50 - Classic EPLD, 900 Gates, 50ns PLCC-44 | Intel
The Intel (formerly Altera) EP910ILC-50 is a member of the Altera Classic EPLD (Erasable Programmable Logic Device) family, delivering 24 macrocells and approximately 900 usable gates in a 44-pin PLCC package. Fabricated on advanced CMOS EPROM technology, it provides high-speed, low-power logic integration with a 50 ns pin-to-pin propagation delay (the "-50" speed grade) and is rated for commercial 5V operation. According to the Altera EP910 datasheet, the device offers 36 user I/O pins plus four dedicated inputs, JTAG/IEEE 1149.1 boundary-scan support on selected speed grades, and global/quad clock networks suitable for state-machine and glue-logic designs. A Classic EPLD is a UV-erasable, electrically programmable logic device that sits in the hierarchy between discrete PAL/GAL and modern SRAM-based CPLDs/FPGAs. Programmable AND/OR macrocell architecture combines PAL-like speed with sum-of-products flexibility, while non-volatile EPROM cells retain configuration without external boot memory. Compared with contemporary SRAM FPGAs, Classic EPLDs offer instant-on behavior, deterministic timing, and excellent design security. Key features of the EP910ILC-50 include 24 macrocells, 12 dedicated input pins, 24 I/O pins arranged in four LAB-style groups, a 50 ns tpd commercial timing specification, and a 5V VCC supply typical of the Classic family. The device is housed in a J-leaded PLCC-44 surface-mount package suitable for socketed programming and field upgrades. Macrocells include configurable flip-flop polarity, output enable control, and product-term sharing for efficient state-machine implementation. The EP910 is implemented in 0.8 um-class CMOS EPROM process technology with a 5V programming algorithm and supports up to 100 erase/program cycles. Built-in JTAG (IEEE 1149.1) boundary-scan test logic on selected speed grades simplifies board-level test, and the device is supported by the Altera MAX+PLUS II development environment (legacy). The Classic architecture delivers predictable timing across commercial and industrial temperature ranges, making it well suited for replacement and maintenance of legacy designs. Typical applications include address decoding and bus interfacing in 5V microprocessor systems, peripheral glue logic in industrial controllers, state-machine controllers in instrumentation, and legacy telecom/military replacement programs where the original Altera Classic design must be replicated. The instant-on non-volatile configuration makes the EP910ILC-50 attractive for safety-critical and security-sensitive designs that cannot tolerate FPGA configuration latency. When designing with this part, note that the Classic family is in legacy/last-time-buy status with most speed grades and is increasingly hard to source. Engineers maintaining existing EP910 designs should qualify the EP910ILC-50 or a pin-compatible Classic variant, and consider migrating to MAX 7000-series CPLDs for new designs. This page synthesizes distributor pricing, datasheet-cited parameters, pin-compatible drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone.
EP910ILI-25 - 24-Macrocell Classic EPLD, 28ns, PLCC-44 | Altera
The Altera EP910ILI-25 is a Classic EPLD (Erasable Programmable Logic Device) from the EP910 series, providing 24 macrocells with 12 dedicated inputs and 24 bidirectional I/O lines, packaged in a 44-pin Plastic Leaded Chip Carrier (PLCC). It is implemented in CMOS technology with a PAL-type architecture, supports up to 240 product terms across the programmable AND/OR array, and is specified with a 25 ns propagation delay (tPD) measured at room temperature. What is a Classic EPLD? A Classic EPLD is an early-generation erasable programmable logic device that combines multiple PAL-type macrocells into a single package, allowing designers to replace several discrete 24-pin PALs with one part. Within the broader programmable logic hierarchy, an EPLD sits between simple SPLDs (single PAL/GAL devices) and modern CPLDs/FPGAs. EPLDs use EPROM, EEPROM, or flash memory cells to store the fuse map, are non-volatile, and are typically programmed once via a hardware programmer such as the Altera MAX+PLUS II development system. Key features include a 25 ns pin-to-pin propagation delay, 24 macrocells interconnected by a global bus, 12 dedicated input pins, 24 I/O pins, up to 240 product terms, an on-board JTAG-compatible logic test circuitry for AC verification during production flow, and CMOS process technology that yields low power consumption. The part uses an erasable windowed package variant, allowing the device to be erased with UV light and re-programmed. The EP910ILI-25 architecture uses a programmable AND array feeding a fixed OR array within each macrocell, with each macrocell containing a flip-flop, output enable, and feedback path. Macrocells share a single global interconnect bus that routes any macrocell output back to any other macrocell input, providing flexible logic implementation across the 24-cell fabric. This architecture is optimized for state machines, address decoding, and glue-logic replacement in 5V systems. Typical applications include TTL/CMOS logic integration, address decoding for microprocessor systems, state machine implementation, peripheral interface glue logic, and bus arbitration logic. The industrial temperature grade (-40C to +85C) and 5V operation make it suitable for legacy industrial control systems and 5V-only designs. When designing with the EP910ILI-25, ensure your logic fits within 24 macrocells and 240 product terms; over-utilization forces the fitter to share product terms, which can degrade timing. Use the Altera MAX+PLUS II development environment for design entry, simulation, and programming, as this is the only officially supported toolchain for the Classic EPLD family. This page synthesizes distributor inventory, cross-reference alternatives from the EP910 series, and practical design notes not found in the legacy datasheet, helping engineers evaluate supply options for this mature, EOL-prone part.
EP910IPC-12 - Classic 24-Macrocell EPLD, 5V, 40-Pin PDIP | Altera
The Altera EP910IPC-12 is a member of the Classic EPLD family, a high-performance CMOS Erasable Programmable Logic Device with a 24-macrocell array, 450 usable gates, and a 76.9 MHz maximum operating frequency. Housed in a 40-pin PDIP (Plastic DIP) through-hole package and specified for 12 ns propagation delay with 5V nominal VCC, the EP910IPC-12 provides reconfigurable combinational and registered logic for glue-logic, state-machine, and bus-interface applications. An EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic device that combines the flexibility of a PLD with on-chip macrocell architecture. In the broader hierarchy, the EPLD sits between simple PAL/GAL devices and larger CPLDs/FPGAs - it offers erasable reprogrammability, deterministic timing, and a fixed but flexible macrocell structure suited to medium-complexity logic replacement. The Classic family from Altera was the precursor to the MAX series and introduced 24 macrocells with predictable pin-to-pin delays, making them suitable for synchronous and asynchronous state machines, address decoding, and peripheral control. Key features of the EP910IPC-12 include 24 macrocells, 10 dedicated input pins, 24 I/O pins, 12 ns pin-to-pin propagation delay (tPD), and a 76.9 MHz internal fMAX for registered logic. The device supports in-system UV-erase (windowed versions) or one-time-programmable (OTP) operation, includes a JTAG-style test mode for functional verification during production, and offers 3.3V/5V mixed-mode I/O via the Altera MAX+PLUS II development environment. Architecturally, the EP910IPC-12 uses a sum-of-products PLA feed driving a flexible macrocell flip-flop array, with global and per-macrocell clock controls. Each macrocell contains a programmable D/T/J-K flip-flop, output enable polarity, and feedback selection, allowing the device to implement registered, combinatorial, and I/O-buried logic with deterministic 12 ns delays. The 5V VCC and TTL-compatible I/O make the part compatible with legacy 74-series logic and 5V microprocessors. Typical applications include bus-interface and address-decoding glue logic for 8086/68000-era microprocessor systems, peripheral controllers, custom state machines, board-level timing generators, and legacy replacement of 74LS/74ALS discrete logic. The 40-pin PDIP package simplifies through-hole prototyping and field-repair scenarios. When designing with the EP910IPC-12, note that the Classic EPLD uses the legacy MAX+PLUS II toolchain (modern Quartus does not directly target this family). For new designs the MAX series (EPM7128, EPM3064) is recommended, but the EP910IPC-12 remains a useful part for sustaining legacy 5V systems. This page synthesizes distributor availability, parametric drop-in alternatives from the EP910 family, and design notes not found in the original datasheet.
EP910IPC-15 - Altera Classic EPLD 24-Macrocell 15ns DIP-40
The Altera EP910IPC-15 is a Classic-series Erasable Programmable Logic Device (EPLD) from the EP910 family, offering 24 macrocells, 12 dedicated inputs, and 24 I/O pins interconnected through a programmable global bus in a 40-pin PDIP (DIP-40) through-hole package. Per Altera/Intel datasheet documentation for the EP910 series, the part is specified at a 15 ns pin-to-pin propagation delay and operates from a single 5 V supply (4.75 V to 5.25 V), targeting glue-logic integration where discrete TTL/CMOS gates would otherwise consume board area. A Classic EPLD is a CMOS-based programmable logic device that combines the integration density of a small PLD with the simple, non-volatile architecture of a PAL. The EP910 sits in the hierarchy of programmable logic between simple SPLDs (PAL/GAL, tens of gates) and complex PLDs/early CPLDs (hundreds of macrocells), and is fabricated on an advanced CMOS process that gives it the low-power, high-noise-immunity characteristics engineers expect from CMOS PAL replacements. The "Classic" label distinguishes this family from later MAX-series CPLDs that added in-system programmability and higher macrocell counts. Key features include a 15 ns worst-case combinatorial propagation delay (tPD), 24 macrocells with 240 product terms for sum-of-products logic, two global clock networks for registered logic, and a typical standby current in the milliamp range on a 5 V rail. Programming is performed via a standard Altera EPLD programmer using a JEDEC fuse map, and the device is erasable in a UV chamber (windowed CERDIP versions exist in the family), making it suitable for prototyping before committing to one-time-programmable (OTP) plastic DIP. Architecture-wise, the EP910 uses a PAL-type AND-OR structure with a global interconnect: each macrocell owns a fixed fan-in product term group that feeds an OR array, then a configurable output cell that can be registered or combinatorial. The "IPC" suffix denotes the industrial temperature grade with a ceramic/plastic 40-pin DIP package, and the "-15" speed grade places it in the mid-speed bin of the EP910 series alongside the -25 and -35 variants. Typical applications include board-level glue logic replacement, state-machine decoding, address decoding in microprocessor systems, peripheral interface adapters, and bus-arbitration controllers in industrial control and instrumentation equipment. The DIP-40 footprint is favored in legacy through-hole designs and breadboard prototyping. When designing with the EP910IPC-15, ensure the supply rail stays within 4.75 V to 5.25 V and respect the 15 ns timing budget across temperature. Unused I/O pins should be left floating or tied to a defined logic level per the Altera EPLD design guidelines to minimize quiescent current draw. This page synthesizes distributor stock, pricing, and drop-in alternatives not consolidated on the original Altera datasheet, enabling faster sourcing and second-source decisions for the EP910 Classic EPLD family.
EP910IPC-25 - 24 Macrocell Classic EPLD 25ns PDIP-40 | Intel
The Intel EP910IPC-25 is a 24-macrocell Classic EPLD (Erasable Programmable Logic Device) from Altera's EP910 family, housed in a 40-pin PDIP (Plastic DIP) through-hole package with a 25 ns propagation delay. It provides 450 usable gates, 24 macrocells interconnected by a global bus, 12 dedicated inputs, and 24 bidirectional I/O lines for up to 36 total inputs and 24 outputs, with 240 product terms. An EPLD (Erasable Programmable Logic Device) is a type of programmable logic that combines the non-volatile, field-programmable architecture of an EPROM with sum-of-products logic arrays. EPLDs sit in the broader taxonomy as: EPLD -> PLD (Programmable Logic Device) -> programmable logic -> digital IC -> semiconductor. They were widely deployed before modern CPLDs and FPGAs dominated new designs, and they remain valuable for legacy system maintenance, repair, and industrial control applications where pin-compatible replacement of an original Classic EPLD is required. Key features include 25 ns maximum propagation delay (tPD), 5 V single-supply CMOS operation, 240 product terms, JTAG-compatible in-system verification, and on-board logic test circuitry for AC specification validation during production flow. The EP910 family is supported by the MAX+PLUS II development system, allowing engineers to capture schematics, synthesize logic, and program the device via the Altera programming algorithm. The EP910IPC-25 uses a PAL-type architecture with a programmable AND/OR array driving 24 macrocell flip-flops. Each macrocell can be configured as D, T, JK, or SR flip-flop with individual product-term clock, reset, and preset control. The 'I' temperature grade designates commercial (0C to 70C) operation, while the 'PC' package suffix denotes the 40-pin plastic DIP. The '25' suffix identifies the speed grade (25 ns tPD). This combination of CMOS low power and TTL-compatible I/O makes the EP910 well-suited for glue-logic replacement in industrial bus interfaces and peripheral controllers. Typical applications include legacy glue-logic replacement in industrial controllers, address decoding and interrupt steering in 5 V bus systems, peripheral interface state machines, and replacement of discrete 74-series TTL in long-life-cycle equipment. Designers maintaining older Intel 8086/8088 or Motorola 68000 systems often turn to the EP910 family when they need a programmable alternative to a board full of discrete logic. When designing with the EP910IPC-25, ensure the 5 V supply rail is well-decoupled with 0.1 uF ceramic capacitors near each VCC pin and that all unused I/O pins are tied to a defined logic level. The device is one-time programmable (OTP) via UV window or programmer socket, so the design must be verified in simulation before committing to silicon. This page synthesizes distributor stock, pricing as of 2026-09-10, pin-compatible drop-in alternatives from the same Classic EPLD family, and practical design notes for engineers maintaining legacy 5 V programmable-logic systems - information not consolidated on the manufacturer product page.
EP910IPC-50 - Altera Classic EPLD, 50ns, 24 I/O, DIP-40 | Altera
The Altera EP910IPC-50 is a member of the Classic EPLD family of high-performance CMOS Erasable Programmable Logic Devices, providing 24 user I/O pins and a 50ns maximum propagation delay in a 40-pin ceramic DIP (IPC) package. The IPC suffix denotes the industrial-grade ceramic DIP variant, while the -50 speed grade specifies the tPD tier. The Classic EPLD family was fabricated on advanced CMOS technology and offered a flexible, low-power solution for high-speed logic integration in the late 1980s and 1990s. An EPLD (Erasable Programmable Logic Device) is a type of programmable logic IC that combines AND/OR arrays with output macrocells, sitting in the historical taxonomy between PALs and modern CPLDs. EPLDs use UV-erasable EPROM cells to retain configuration, and they belong to the broader family of programmable logic devices that today includes CPLDs and FPGAs. As a Classic-series part, the EP910IPC-50 represents an early generation of CMOS programmable logic, optimised for low static power consumption and predictable, deterministic pin-to-pin timing. Key features of the EP910IPC-50 include 24 available I/O pins, a maximum propagation delay of 50ns (with tCO of 35ns), an internal flip-flop toggle frequency around 26 MHz, and 5V (4.75V to 5.25V) single-supply operation. The device is housed in a 40-pin ceramic DIP (windowed) package for UV erasure and reprogramming, and is specified over an industrial temperature range of -40C to +85C. Output drive current is sufficient for standard TTL/CMOS loads, and the architecture supports combinatorial and registered logic with separate configurable output macrocells. The EP910 uses a sum-of-products architecture with 72 product terms distributed across its macrocells, allowing designers to replace multiple discrete SSI/MSI logic packages with a single EPLD. The device is programmed using a standard EPROM programmer and erased via UV exposure through the ceramic window, which is the defining characteristic of the IPC (Industrial Pin-grid Ceramic) windowed package. The Classic EPLD family was popular for glue logic, bus decoding, and state-machine applications in the 1980s and early 1990s. Typical applications for the EP910IPC-50 include bus interface and address decoding in legacy microprocessor systems, replacement of discrete TTL/CMOS glue logic, state-machine and sequencer logic in industrial controllers, and prototyping of custom registered logic. It is also commonly used in educational settings where UV-erasable windowed packages are advantageous for repeated lab cycles. When designing with the EP910IPC-50, ensure that all unused I/O pins are configured correctly per the datasheet, and verify that the timing model (tPD, tCO, tSU) meets the target system clock budget. Because the part uses EPROM cells, the device is not in-system programmable and requires a separate EPROM programmer and UV eraser for design iteration. This part is now considered legacy and is typically sourced through distributors stocking remaining inventory.
EP910JC-30 - 30ns 24-Macrocell Classic EPLD | Intel / Altera
The Altera (now Intel) EP910JC-30 is a 30ns Classic-series Erasable Programmable Logic Device (EPLD) belonging to the MAX-prefix family of pre-CPLD programmable logic, packaged in a 44-pin windowed ceramic J-leaded chip carrier (CQCC-44 / JLCC-44) with UV-erasable EPROM technology. An EPLD (Erasable Programmable Logic Device) is a one-time-factory-or-window-erasable member of the programmable logic hierarchy that sits below modern CPLDs and FPGAs in capacity. The category chain is: programmable logic device (PLD) -> EPLD -> MAX-style architecture -> CMOS EPROM-based logic block. EPLDs historically served as glue-logic replacements for multiple 74-series TTL/CMOS packages in bus-interface, address-decoding and state-machine designs. Key headline parameters: 30 ns maximum propagation delay (tpd), 33.3 MHz maximum internal clock frequency (Fmax), 24 macrocells, 36 inputs, 240 product terms, and 10 dedicated output macrocells. The device operates from a single 5V supply and is built on a non-volatile UV-erasable CMOS process, so logic configuration is retained without a configuration memory download at power-up. Architecturally, the EP910 combines a programmable AND array feeding a fixed OR array with output macrocells that can be configured as registered, combinatorial, or bidirectional I/O. The 24 macrocells are organized to deliver up to 10 dedicated outputs plus 24 I/O pins, and the 240 product terms support sum-of-product logic minimization typical of state-machine and decoder implementations. Typical applications include legacy glue-logic replacement for 74LS/74HC discrete packages, microprogram sequencers, bus address decoders, peripheral chip-select generators, and CMOS-to-TTL level translation interfaces. Because the part is UV-erasable, it is favored for prototyping and field-reprogrammable industrial controllers. When designing with this part, plan for a 200 mA typical Icc budget, provide a 0.1 uF decoupling capacitor on every VCC pin pair, and respect the 30 ns propagation delay when computing worst-case setup margins. Logic fitting must observe the 240 product-term limit per macrocell to avoid synthesis overflow. This page combines distributor pricing, drop-in alternatives, and design notes not aggregated on the manufacturer datasheet.