EP910ILC-15N - 450 Gate 24-Macrocell Classic CPLD, 15ns, 5V, 44-PLCC | Altera
Référence : EP910ILC-15N ✗ Fin de vie| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $18.5 | $18,50 |
| 10 | $16.2 | $162,00 |
| 100 | $13.75 | $1 375,00 |
| 500 | $11.4 | $5 700,00 |
| 1 000 | $9.85 | $9 850,00 |
EP910ILC-15N Présentation
A CPLD (Complex Programmable Logic Device) is a non-volatile, instant-on programmable logic device that sits between simple SPLDs/GALs and higher-density FPGAs in the programmable logic hierarchy. CPLDs use a classic AND/OR plane architecture with a deterministic interconnect, EEPROM or EPROM configuration memory, and predictable timing that is independent of routing path. They are typically chosen over FPGAs when designs require fast input-to-output response, simple glue-logic integration, power-on instant-on behaviour without an external boot PROM, and I/O-rich, low-density logic capacity. The Classic family from Altera was an early-generation architecture that combined low static power with simple development tools such as the MAX+PLUS II environment.
Key features of the EP910ILC-15N include 24 macrocells partitioned into logic blocks, 36 user I/O pins, 16 dedicated input pins, JTAG-compliant IEEE 1149.1 boundary-scan test support, and programmable output slew-rate control. The 15 ns speed grade enables combinational logic at moderate clock rates suitable for bus-interface, address-decoding, and peripheral-control tasks.
Internally, the device uses a sum-of-products architecture with each macrocell containing a flip-flop and programmable output polarity. The 5 V CMOS I/O structure is TTL-compatible on inputs and capable of sinking 12 mA per output, allowing direct interface with 74-series logic, microprocessors, and SRAM without external buffers. The PLCC-44 package offers socketability for prototyping and field upgrades.
Typical applications include legacy ISA/PCI bus interface logic, address decoding and glue logic for 8051/Microprocessor systems, state-machine controllers, and peripheral bus arbiter replacement. The instant-on non-volatile configuration makes the EP910ILC-15N particularly attractive in industrial-control and military-aerospace designs where boot-time predictability is essential.
When designing with this part, observe the 5 V VCC tolerance and provide adequate decoupling (0.1 uF per supply pin plus a bulk 10 uF tantalum). For high-speed designs, respect the 15 ns tPD timing budget and use the JTAG port for in-system programming.
This page synthesises distributor pricing from Rochester Electronics and other sources, drop-in alternative MPNs, and practical design notes not consolidated in the original manufacturer datasheet.
Alternatives de remplacement direct pour EP910ILC-15N — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec EP910ILC-15N (même facteur de forme et même empreinte) — différant par Package, Mounting Type, Operating Temperature, Family, Product Type.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
EP910ILC-12
✅ Remplacement direct✓ En stock
$12.4 / unité
Voir la fiche technique →EP910ILC-15
✅ Remplacement direct✓ En stock
$16.1 / unité
Voir la fiche technique →EP910DC-15
✅ Remplacement direct ⚠️ Spécifications non vérifiées✓ En stock
$10.75 / unité
Voir la fiche technique →EP910DM/883B
✅ Remplacement direct✓ En stock
$180 / unité
Voir la fiche technique →EP910ILC-20
✅ Remplacement direct ⚠️ Spécifications non vérifiées📋 Alternative de référence (hors catalogue)
EP610ILC-10
✅ Remplacement direct✓ En stock
$7.2 / unité
Voir la fiche technique →EP910ILC-15N Valeurs maximales et caractéristiques électriques
| Family | Classic |
| Product Type | CPLD (Complex Programmable Logic Device) |
| Logic Gates | 450 |
| Macro Cells | 24 |
| Maximum Propagation Delay (tPD) | 15 ns |
| Maximum Operating Frequency | 66.6 MHz |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) |
| User I/O Pins | 36 |
| Dedicated Input Pins | 16 |
| Boîtier | PLCC-44 (J-lead, surface mount) |
| Type de montage | Surface Mount |
| Température de fonctionnement | 0 C to +70 C (commercial) |
| Process Technology | CMOS EPROM (one-time programmable) |
| JTAG Support | IEEE 1149.1 boundary-scan |
| Statut RoHS | Compliant |
| Programming | EPROM / JTAG (Classic EP-series) |
Configuration des broches de EP910ILC-15N
| Broche 1 | I/O — Bidirectional user I/O pin (Macrocell block) |
| Broche 2 | I/O — Bidirectional user I/O pin |
| Broche 3 | I/O — Bidirectional user I/O pin |
| Broche 4 | I/O — Bidirectional user I/O pin |
| Broche 5 | I/O — Bidirectional user I/O pin |
| Broche 6 | I/O — Bidirectional user I/O pin |
| Broche 7 | I/O — Bidirectional user I/O pin |
| Broche 8 | I/O — Bidirectional user I/O pin |
| Broche 9 | GND — Ground |
| Broche 10 | I/O — Bidirectional user I/O pin |
| Broche 11 | I/O — Bidirectional user I/O pin |
| Broche 12 | I/O — Bidirectional user I/O pin |
| Broche 13 | I/O — Bidirectional user I/O pin |
| Broche 14 | I/O — Bidirectional user I/O pin |
| Broche 15 | I/O — Bidirectional user I/O pin |
| Broche 16 | I/O — Bidirectional user I/O pin |
| Broche 17 | I/O — Bidirectional user I/O pin |
| Broche 18 | I/O — Bidirectional user I/O pin (dedicated input capable) |
| Broche 19 | I/O — Bidirectional user I/O pin (dedicated input capable) |
| Broche 20 | I/O — Bidirectional user I/O pin (dedicated input capable) |
| Broche 21 | I/O — Bidirectional user I/O pin (dedicated input capable) |
| Broche 22 | GND — Ground |
| Broche 23 | I/O — Bidirectional user I/O pin (dedicated input capable) |
| Broche 24 | I/O — Bidirectional user I/O pin (dedicated input capable) |
| Broche 25 | I/O — Bidirectional user I/O pin (dedicated input capable) |
| Broche 26 | I/O — Bidirectional user I/O pin (dedicated input capable) |
| Broche 27 | I/O — Bidirectional user I/O pin (dedicated input capable) |
| Broche 28 | I/O — Bidirectional user I/O pin (dedicated input capable) |
| Broche 29 | I/O — Bidirectional user I/O pin (dedicated input capable) |
| Broche 30 | I/O — Bidirectional user I/O pin (dedicated input capable) |
| Broche 31 | I/O — Bidirectional user I/O pin (dedicated input capable) |
| Broche 32 | I/O — Bidirectional user I/O pin (dedicated input capable) |
| Broche 33 | GND — Ground |
| Broche 34 | I/O — Bidirectional user I/O pin |
| Broche 35 | I/O — Bidirectional user I/O pin |
| Broche 36 | I/O — Bidirectional user I/O pin |
| Broche 37 | I/O — Bidirectional user I/O pin |
| Broche 38 | I/O — Bidirectional user I/O pin |
| Broche 39 | I/O — Bidirectional user I/O pin |
| Broche 40 | I/O — Bidirectional user I/O pin |
| Broche 41 | I/O — Bidirectional user I/O pin |
| Broche 42 | I/O — Bidirectional user I/O pin |
| Broche 43 | TDI — JTAG Test Data In |
| Broche 44 | VCC — +5 V supply |
Applications typiques
EP910ILC-15N convient pour 6 applications: Legacy ISA Bus Address Decoding, 8051 Microprocessor Peripheral Glue Logic, Industrial Control State Machine, Peripheral Bus Arbiter / Controller, Military / Aerospace Avionics (via MIL-STD-883 grade), Retro Computing Replica Boards.
Legacy ISA Bus Address Decoding
The EP910ILC-15N's 15 ns tPD and 36 user I/O pins make it well suited for legacy ISA-bus address decoding in industrial motherboards and retro-computing hardware. Its 5 V TTL-compatible I/O interfaces directly to 74LS245 buffers and the ISA bus without external level shifting, while 24 macrocells provide sufficient capacity for full 24-bit address decode and chip-select logic. The instant-on non-volatile configuration eliminates the boot-time delay of SRAM-based FPGAs, ensuring that address and chip-select signals are valid at power-on - critical for legacy peripherals that expect deterministic power-on behaviour.
Recommandé
8051 Microprocessor Peripheral Glue Logic
The EP910ILC-15N integrates the address latching, chip-select decoding, and I/O expansion typically required around an 8-bit 8051 family processor. With 24 macrocells it can replace 4-6 discrete 74HC/74LS PALs, freeing PCB real-estate and reducing the BOM. The 15 ns tPD easily satisfies the 8051's 12 MHz ALE-to-valid timing, and the 5 V single-supply design matches the 8051's VCC rail directly. JTAG boundary-scan support assists bed-of-nails in-circuit test, lowering manufacturing test cost for medium-volume embedded products.
Recommandé
Industrial Control State Machine
The EP910ILC-15N's deterministic 15 ns timing and EPROM-based non-volatile configuration make it ideal for hard-real-time industrial-control state machines where predictable response is more important than raw gate count. Applications include conveyor sortation logic, packaging-machine sequencers, and CNC auxiliary controllers. The 5 V tolerance and 0-70 C commercial temperature range suit panel-mount enclosed cabinets, while the PLCC-44 package supports socketed replacement in fielded equipment without desoldering. JTAG allows in-system reprogramming during factory commissioning.
Recommandé
Peripheral Bus Arbiter / Controller
The EP910ILC-15N provides centralised bus arbitration and peripheral control in multi-master systems. With 24 macrocells, the device can implement a multi-port arbiter, interrupt controller, and timing-generator in a single chip, replacing dozens of 74LS-series TTL parts. The 5 V TTL-compatible I/O directly interfaces with DMA controllers, SCSI adapters, and other legacy peripherals. The 15 ns tPD comfortably arbitrates within standard ISA / VMEbus cycle times, while the non-volatile EPROM configuration means the arbiter is operational at the first clock edge after power-up.
Recommandé
Military / Aerospace Avionics (via MIL-STD-883 grade)
While the EP910ILC-15N itself is a commercial-grade part, the same EP910 die is offered in MIL-STD-883B processing (EP910DM/883B) in the same PLCC-44 footprint, with a -55 C to +125 C operating range. This makes the Altera Classic EP910 family a long-standing choice for legacy avionics, weapon-system test equipment, and space-grade subsystems where instant-on non-volatile logic and a MIL-PRF-38535 pedigree are required. System designers standardise on the EP910 footprint to allow seamless substitution between commercial prototypes and flight-qualified hardware.
Recommandé
Retro Computing Replica Boards
The EP910ILC-15N is popular among retro-computing hobbyists restoring 1980s-era arcade boards, vintage PCs, and classic gaming consoles such as the Commodore 64 cartridge expansions and early arcade logic boards. Its 5 V supply matches original-system rails, and its socketable PLCC-44 package lets hobbyists swap and reprogram (via OTP) replacement parts easily. The 15 ns tPD meets the timing budgets of 4-8 MHz original-era bus architectures. Reproducing the original Altera Classic design in FPGA is impractical for authenticity, so genuine EP910 parts are in continuous small-volume demand.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour EP910ILC-15N — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | EP910ILC-12 | EP910ILC-15 | EP910DC-15 | EP910DM/883B | EP910ILC-20 | EP610ILC-10 |
|---|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | PLCC-44 | PLCC-44 - same | PLCC-44 - same | PLCC-44 - same | PLCC-44 - same | PLCC-44 - same | PLCC-44 - same |
| Logic Gates | 450 | 450 | 450 | 450 | 450 | 450 | 300 |
| Macro Cells | 24 | 24 | 24 | 24 | 24 | 24 | 16 |
| Propagation Delay (tPD) | 15 ns | 12 ns (faster) | 15 ns (identical) | 15 ns (identical) | 15 ns (identical) | 20 ns (slower) | 10 ns (faster) |
| Max Frequency (fMAX) | 66.6 MHz | 83.3 MHz | 66.6 MHz | 66.6 MHz | 66.6 MHz | 50 MHz | 100 MHz |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Operating Temperature | 0 C to +70 C (commercial) | 0 C to +70 C | 0 C to +70 C | 0 C to +70 C | -55 C to +125 C (military) | 0 C to +70 C | 0 C to +70 C |
| Programming Technology | EPROM (OTP) | EPROM (OTP) | EPROM (OTP) | EPROM (OTP) | EPROM (OTP) | EPROM (OTP) | EPROM (OTP) |
Principaux différenciateurs
- Broader operating-temperature availability via MIL-STD-883B variant (vs EP910ILC-15N (commercial) vs EP910DM/883B (military))
- Faster -12 speed grade available in identical footprint (vs EP910ILC-15N vs EP910ILC-12)
- Instant-on non-volatile configuration vs SRAM-based FPGAs (vs EP910ILC-15N vs typical SRAM FPGA)
Notes de conception
Estimated: At 5 V VCC and typical ICC of approximately 100 mA (idle) to 150 mA (active), total power dissipation is 0.5-0.75 W per device. Place one 0.1 uF ceramic decoupling capacitor at each VCC pin (pin 44) plus one bulk 10 uF tantalum near the package. For multi-CPLD designs, add a ferrite bead on the supply rail to suppress switching-current-induced noise coupling into adjacent analog sections.
Route JTAG signals TDI/TDO/TMS/TCK as a four-wire bus with 10 kohm pull-ups on TMS and TCK. Keep the JTAG chain under 6 inches total length to avoid signal-integrity issues. Use a 44-pin PLCC socket (e.g. 3M 8444-21B1-RK-TB or Aries 44-3554-10) for prototype builds to simplify EPROM-OTP replacement during design iteration. Reserve PCB area for the JTAG header (2x5 0.1 inch pin-header) at board edge for programming access.
Do not confuse the EP910 family (one-time-programmable EPROM, 5 V VPP) with the EPM910 or EPM3060 family (in-system-programmable EEPROM). Programming voltage and algorithm differ. For designs that require field upgradeability, choose EPM-series MAX CPLDs instead. Verify in MAX+PLUS II that the target device is selected as EP910 (not EPM910) before generating the .POF file to avoid programming-voltage mismatch and permanent device damage.
For high-speed designs using the 15 ns speed grade, place the EP910ILC-15N within 2 inches of its companion bus devices to minimise stub-length-induced reflections. Use a continuous ground plane under the PLCC-44 socket; avoid signal traces under the socket cavity. Pin 1 identification: pin 1 is located at the top-left of the package with the chamfered edge down, matching standard PLCC JEDEC MS-018 pin numbering.
Informations de conformité
RoHS compliance per GlobalSpec datasheet summary. Lead-free finish on -N suffix variant. AEC-Q100 is not applicable (commercial/industrial logic device, not automotive-qualified). Military-grade MIL-STD-883B variant (EP910DM/883B) is available for defence applications in the same PLCC-44 footprint.
