FPGA & CPLD
Produits (6666)
EP910JC-35 - 24-Macrocell Classic EPLD, 38ns, 44-Pin PLCC | Altera
The Altera EP910JC-35 is a high-performance 24-macrocell erasable programmable logic device (EPLD) from the Classic EPLD family, housed in a 44-pin plastic J-leaded chip carrier (PLCC) package with a commercial temperature grade of 0C to 70C. It features a maximum propagation delay of 38 ns and a maximum clock frequency of approximately 28.6 MHz, with 36 inputs and 24 I/O lines for glue-logic integration in 5 V systems. The device operates from a single 4.75 V to 5.25 V supply, drawing from Altera's Classic EP910 macrocell architecture originally introduced by Intel's programmable logic division. An EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic IC that combines PAL/GAL-like AND/OR arrays with user-programmable macrocell flip-flops. EPLDs sit within the broader programmable logic hierarchy below modern FPGAs and CPLDs but above simple SPLDs, providing deterministic 5 V CMOS logic with zero-power standby and UV-erasable (windowed) or one-time-programmable (OTP) configurations. The EP910 family occupies the mid-density tier with 24 macrocells and roughly 900 usable gates, bridging 22V10-class SPLDs and the larger EP1800/EP1810 Classic devices. Key features of the EP910JC-35 include 24 macrocells, 36 inputs, 24 bi-directional I/O pins, 38 ns maximum pin-to-pin propagation delay (commercial grade, -35 speed grade), and a single 5 V supply. The device supports both combinatorial and registered logic, with per-macrocell configurable D/T/JK flip-flops. Its deterministic timing makes it well suited for address decoding, bus interfacing, and state-machine replacement of discrete 74LS logic. The EP910JC-35 architecture is built on Altera's CMOS Classic EPROM technology, providing non-volatile configuration and CMOS-level drive capability. The PLCC-44 package provides socketable assembly for prototyping and easy field replacement. Compared with PAL/GAL parts, the EP910 integrates wider sum-of-products arrays and output logic macrocells, enabling more complex state machines within a single device. Typical applications include industrial automation controllers, telecommunications line cards, test and measurement equipment, and address-decoding glue logic in microprocessor systems. Engineers often select the EP910JC-35 to consolidate scattered TTL/CMOS logic or to implement custom peripheral interfaces without the cost and power of an FPGA. When designing with this device, note that the EP910 is a legacy Classic EPLD and is not footprint-compatible with modern MAX II/MAX V CPLDs. Use a 44-pin PLCC socket to simplify prototyping and field service. Ensure input edge rates meet the Classic EPLD tR/tF limits to avoid AC noise-induced double clocking. This page synthesizes distributor pricing, legacy EPLD alternatives, and practical migration guidance not found in the original Altera datasheet. Pricing is referenced as of 2026-09-10.
EP910JM-40 - 24-Macrocell UV EPLD, 40ns | Altera Classic
The Altera EP910JM-40 is a high-performance 24-macrocell UV-erasable programmable logic device (EPLD) from the Altera Classic EPLD family, supplied in a ceramic J-lead (JLCC) windowed package and specified for a 40 ns propagation delay. It targets high-speed CMOS logic integration in glue-logic, bus-interface, state-machine, and decoder applications where deterministic combinational and registered logic with low power consumption is required. The part is a UV PLD with PAL-type architecture and CMOS fabrication, offering 24 macrocells interconnected by a global bus. A UV Erasable Programmable Logic Device (UV EPLD) is a one-time-programmable (erasable via ultraviolet light through the ceramic window) PLD built on CMOS technology, belonging to the broader category of programmable logic devices (PLD) > programmable logic > logic ICs > integrated circuits (ICs). Compared with later SRAM-based FPGAs, EPLDs are non-volatile, deterministic, and feature a predictable timing model with pin-to-pin delays independent of internal routing. The EP910 sits in the mid-density Classic family, between the EP610 (16 macrocells) and EP1810 (48 macrocells), and is well suited to glue-logic integration on systems where a few hundred gates of custom logic replace discrete 74-series TTL. Key features include 24 macrocells, 12 dedicated inputs, 24 I/O lines (36 inputs / 24 outputs maximum), 240 product terms, two external clock inputs, and CMOS low-power operation. The J-suffix (windowed ceramic JLCC) package enables field erasure and reprogramming under a UV lamp, while the -40 speed grade designates a 40 ns tPD from input pin to output pin. These specifications make the EP910JM-40 a common drop-in part for legacy designs originally prototyped on Altera or third-party EPLD toolchains. Architecturally, the EP910 uses a sum-of-products AND/OR array feeding 24 output macrocells, each with a programmable register, output enable, and feedback path. The global bus distributes 12 dedicated inputs to all macrocells, allowing wide combinational fan-in. Designers compile logic with the Altera MAX+PLUS II or legacy A+PLUS toolchain and program the device with a standard EPROM programmer. Typical applications include address decoding and chip-select generation in 80C186/68k/MIPS designs, bus arbitration glue logic, state-machine controllers for industrial controllers, replacement of multiple 74LS/74F TTL packages, and instrumentation front-panel logic. The 40 ns delay grade suits systems with clock periods of 100 ns or longer (e.g., 10 MHz bus architectures). When designing with this part, ensure the IC socket allows UV erasure through the quartz window, use a 25 ms erasure cycle, and verify with the EP910 family datasheet that the JTAG/programming pinout matches the programmer header.
EP910LC-25 - 24 Macrocells Classic EPLD | Intel | 25ns
The Intel (formerly Altera) EP910LC-25 is a 24-macrocell Classic EPLD from the Altera Classic device family, fabricated on advanced CMOS technology for high-speed, low-power logic integration. It provides 24 macrocells, 16 dedicated input pins, and a tPD of 25 ns, housed in a 28-pin PLCC package, making it suitable for legacy glue-logic and state-machine replacement designs. A Classic EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic device from the late 1980s/early 1990s era, predating modern CPLDs and FPGAs. An EPLD uses EPROM or EEPROM cells to store the configuration and contains a small number of macrocells organized with a fixed AND-OR PLA-style interconnect fabric. In the broader taxonomy, an EPLD sits between a PAL/GAL and a true CPLD, offering more macrocells than simple PALs while remaining simpler than modern SRAM-based FPGAs. The Classic device family targets glue logic, bus decoding, state machines, and address decoding where moderate complexity is required. Key features of the EP910LC-25 include 24 macrocells of programmable logic, 16 dedicated inputs, 25 ns pin-to-pin propagation delay, and CMOS technology for low power consumption. The device supports in-system programmability via the Altera programming tools of its era and is offered in a plastic-leaded chip carrier (PLCC) surface-mount package. The EP910LC-25 architecture uses a PLA-style AND-OR array feeding output macrocells with configurable flip-flops. Fabricated on CMOS, the part draws low standby current and is suitable for battery-backed or always-on legacy systems. With 16 dedicated inputs and I/O architecture, it is appropriate for address decoding and small state-machine duties. Typical applications include legacy glue logic in industrial controllers, address decoding for microprocessor systems (8086, 68k, MIPS), bus arbitration, state machines in telecom backplanes, and replacement of discrete TTL/CMOS logic on older boards. The wide operating voltage range and CMOS design make it suitable for both 5V and mixed-voltage legacy systems. When designing with this part, note that it is a legacy device with limited modern tool support. Modern Altera/Intel Quartus does not support the Classic family; designers must use archived MAX+PLUS II or classic Altera tools for programming. Verify long-term availability and consider migration paths. This page consolidates distributor pricing, drop-in alternatives from the same Classic family, and practical design notes for engineers maintaining legacy EP910-based systems or performing long-life-cycle industrial designs.
EP910LC-30 - 24-Macrocell EPLD, 30ns, CMOS PLD | Altera
The Altera EP910LC-30 is a 24-macrocell Erasable Programmable Logic Device (EPLD) with a 30 ns propagation delay, packaged in a 40-pin PDIP through-hole format. It belongs to the Classic EPLD family that established high-performance CMOS programmable logic with 24 macrocells, 36 dedicated inputs, 24 I/O pins, and a maximum of 16 product terms per macrocell for implementing complex combinatorial and registered logic. An EPLD (Erasable Programmable Logic Device) is a non-volatile PLD technology that combines the architectural simplicity of PAL/GAL devices with erasable CMOS storage cells. In the broader taxonomy, EPLD sits between simple PAL-type devices and higher-density CPLDs/FPGAs - offering LSI-equivalent density with TTL-equivalent speed. EP910-series devices are commonly used as glue-logic replacements for discrete TTL/CMOS gate arrays in control, peripheral, and state-machine applications. Key features include 24 macrocells with configurable D/T/JK flip-flops, programmable output polarity, on-chip logic test circuitry for production AC verification, and a maximum toggle frequency of approximately 62 MHz. The device supports in-system programming via the Altera MAX+PLUS II development environment, and is available in commercial (LC) and industrial (LI) temperature grades. The 'C' suffix denotes CMOS process, 'L' denotes low-power, and '-30' denotes the 30 ns pin-to-pin propagation delay. The EP910 architecture uses EPROM-based configuration cells that retain logic when power is removed. Each macrocell contains a programmable AND/OR array, a flip-flop, and an output enable control. The device operates from a single 5 V supply with TTL-compatible I/O. Compared to discrete SSI/MSI logic, a single EP910LC-30 can replace 10-30 standard TTL packages while reducing board area and improving noise immunity. Typical applications include bus-interface glue logic, address decoding, state-machine control, peripheral interfacing, and prototype ASIC replacement. The device is suitable for industrial control systems, telecom peripheral cards, and instrumentation where deterministic 30 ns timing is acceptable. The PDIP-40 package is preferred for through-hole prototyping, hobbyist designs, and legacy system maintenance. When designing with this device, allow for the 30 ns propagation delay when calculating setup/hold margins for downstream flip-flops. Use the Altera MAX+PLUS II software for design entry, simulation, and device programming. Decouple the 5 V VCC pin with a 0.1 uF ceramic capacitor placed within 1 cm of the package, and connect all VCC/GND pins. This page synthesizes distributor pricing, authorized-stock availability through Rochester Electronics, and a drop-in alternatives list (same Altera EP910 family) that DigiKey and Mouser product pages do not aggregate into a single decision-ready view.
EP910LC-30T - 24-Macrocell EPLD, 30ns, 5V, PLCC-44 | Altera
The Altera (Rochester Electronics) EP910LC-30T is a high-performance Classic EPLD with 24 macrocells and 450 usable gates, housed in a 44-pin PLCC (J-lead) package. It is specified at a 30 ns propagation delay (tPD) and operates from a single 5 V supply, offering pin-to-pin compatibility with the broader Altera Classic EPLD family. The "T" suffix denotes Tape and Reel packaging for high-volume assembly. An EPLD (Erasable Programmable Logic Device) is a type of CPLD (Complex Programmable Logic Device) - a non-volatile, reprogrammable digital logic IC that replaces discrete TTL/CMOS glue logic. The EP910 belongs to Altera's Classic Family, which sits in the hierarchy: programmable logic device -> SPLD/CPLD -> EPLD -> Classic EPLD -> EP910 series. EPLDs typically integrate multiple macrocells (each containing a programmable AND/OR array, flip-flop, and I/O) into a single chip with predictable timing, making them ideal for state machines, address decoding, and bus-interface glue logic. Key features of the EP910LC-30T include 24 macrocells providing 450 usable gates, a 30 ns pin-to-pin delay enabling operation up to approximately 33.3 MHz, and 36 user I/O pins with bidirectional programmability. The device is fabricated in CMOS technology, supports in-system UV-erasable programming (windowed ceramic variants) or one-time-programmable (OTP) operation, and includes on-board logic test circuitry for AC parameter verification during production flow. The architecture is built around a programmable AND/OR array feeding 24 flip-flop-equipped macrocells, with output enable and tri-state control per pin. The wide 5 V supply tolerance (4.75 V to 5.25 V) makes it compatible with legacy TTL logic families, while the CMOS process yields low standby current. Programming is performed via the Altera MAX+PLUS II development system, and JTAG-like boundary-scan support is not present on this classic device. Typical applications include legacy glue logic in industrial control systems, address decoding for microprocessor buses, state-machine controllers, and replacement of multiple TTL packages in legacy equipment. The 30 ns grade is well-suited to systems using 8- and 16-bit microprocessors (8086, 68000, Z80) where I/O wait-state insertion is acceptable. When designing with this part, confirm that the 30 ns tPD meets your system's clock-period budget after accounting for setup/hold margins. The PLCC-44 socket enables easy prototyping and field replacement, which is one reason the EP910 family remains in demand for maintaining long-lifecycle industrial and military equipment. This page synthesizes distributor inventory, package-equivalent drop-in alternatives from the Altera Classic EPLD family, and practical design notes not consolidated in the original manufacturer datasheet.
EP910LC-30Y - 24-Macrocell Classic EPLD, 30ns, PLCC-44 | Altera
The Altera EP910LC-30Y is a member of the Classic EPLD family, a high-performance CMOS Erasable Programmable Logic Device delivering 24 macrocells and approximately 450 usable gates in a 44-pin PLCC (Plastic Leaded Chip Carrier) package with a 30ns pin-to-pin logic delay. It is offered in the low-power "LC" speed/power grade and the "Y" extended-reliability processing option, making it suitable for legacy industrial and military systems that require continued long-term supply. A Classic EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic device that combines AND/OR array logic with user-configurable macrocells and output flip-flops. In the broader taxonomy, EPLDs sit between simple PAL/GAL SPLDs and larger CPLDs/FPGAs; they are typically used for glue logic, address decoding, bus interfacing, and state-machine replacement. The EP910LC family specifically targets designs that previously used multiple 20- and 24-pin PAL devices and consolidates them into a single UV-erasable CMOS part with 100% TTL emulation and counter frequencies as high as 100 MHz. Key features include 24 macrocells (each with a programmable flip-flop and I/O architecture), a 30ns tPD (pin-to-pin delay) at the commercial temperature range, low CMOS standby current, and built-in JTAG/loopback test circuitry that allows verification of function and AC specifications during production flow. The PLCC-44 surface-mount package provides socket compatibility with production programmers and board-test fixtures, and the -LC process variant lowers active supply current compared with the standard EP910. The "Y" suffix indicates an extended-reliability processing flow, often required by defense, aerospace, and long-lifecycle industrial programs. Architecturally, the EP910LC-30Y uses a sum-of-products PLA structure with a global interconnect and 24 shared expander terms, giving designers enough flexibility to replace several MSI/SSI logic packages with a single in-system programmable device. Programming is performed via standard Altera programming hardware with the MAX+PLUS II development environment, and the device is one-time-programmable (windowless OTP for production, but the UV-erasable ceramic versions allow design iteration). Typical applications include legacy TTL/CMOS glue-logic consolidation in telecom backplanes, address decoding and wait-state generation in 8086/68k-based embedded systems, industrial PLC and process-control I/O expansion, military and avionics LRUs that need continued support of an Altera Classic part, and FPGA configuration or watchdog logic in mixed-technology boards. The Classic family was historically popular in 1990s-era designs that remain in service or in sustainment programs today. When designing with this device, ensure the EP910LC-30Y is supplied with a stable 5V ±10% rail and that high-frequency output switching currents are decoupled locally. Designers migrating from older PAL/LSI parts should review the MAX+PLUS II fitter reports, because macrocell feedback paths and expander-term sharing affect achievable fMAX. The PLCC-44 socket footprint simplifies field replacement and programmer-based in-system reconfiguration.
EP910LC-32 - 24-Macrocell Classic EPLD, PLCC-32 | Altera
The Altera EP910LC-32 is a 24-macrocell Classic-series Erasable Programmable Logic Device (EPLD) housed in a 32-pin PLCC package with a -32 speed grade. Built on advanced CMOS technology, the EP910LC-32 integrates high-speed, low-power combinational and sequential logic for glue-logic, bus-interface, and state-machine functions, providing an alternative to discrete 7400-series TTL and CMOS gate arrays on legacy 5 V designs. The Classic EPLD family targets pin-compatible upgrades of bipolar PAL/GAL devices while delivering deterministic, non-volatile interconnect and propagation delays in the 15-25 ns range. A Programmable Logic Device (PLD) is a non-volatile semiconductor IC whose AND/OR array and macrocell flip-flops can be configured by the customer after manufacture. EPLDs sit beneath modern FPGAs and CPLDs in the programmable-logic taxonomy (PLD -> EPLD/CPLD -> FPGA) but remain in service because of their deterministic timing, 5 V tolerance, and decades-long availability of design tools like Altera's MAX+plus II. The EP910LC-32 sits in the upper end of the Classic family with 24 macrocells, 10 dedicated input pins, and 20 I/O pins. Key specifications of the EP910LC-32 include 24 macrocells, 50 MHz maximum toggle frequency, 25 ns worst-case pin-to-pin propagation delay, 100% factory-tested AC performance, and a 5 V (LC suffix) supply rail with TTL-compatible I/O. Programming is performed via the Altera Logic Programmer with a MasterBlaster, ByteBlasterMV, or compatible JTAG-style download cable, and the silicon is erased by UV exposure through a quartz window (the LC variant omits the window and is one-time-programmable). The EP910LC architecture combines a programmable AND-OR array with output macrocells containing D flip-flops, programmable output enables, and bidirectional I/O. Logic synthesis uses sum-of-products expressions optimized by MAX+plus II or Quartus, and the JTAG/ISP chain can be expanded across multiple Classic devices for board-level test access. Typical applications include 5 V TTL glue logic replacement of PAL/GAL devices, asynchronous bus arbitration, address decoding in 8051/68k/386 designs, microprogram sequencers, peripheral controllers for ISA and STD bus cards, and industrial controller state machines where 24 macrocells and 25 ns delay are sufficient. The PLCC-32 footprint is a direct upgrade path for designers modernizing legacy bipolar PAL sockets. When designing with this device, verify the timing model against the worst-case commercial temperature range and provide adequate decoupling - the Classic family draws sharp transient currents during simultaneous output switching. Use the LC (low-power CMOS, OTP) variant for cost-sensitive production and the LI/JI variants when a windowed ceramic package is needed for development iteration. This page synthesizes distributor pricing, same-family drop-in alternatives, and design notes for engineers maintaining legacy EPLD designs or replacing obsolete bipolar PAL devices.
EP910LC-35 - 24 Macrocell Classic EPLD, 35ns | Intel/Altera
The Intel/Altera EP910LC-35 is a 24-macrocell CMOS Erasable Programmable Logic Device (EPLD) from the Classic device family, housed in a 44-pin PLCC (J-lead) package and rated at 35ns pin-to-pin propagation delay. It belongs to the EP910 series that delivers 450 usable gates with 24 macrocells and operates from a single 5V supply, making it a direct ancestor of today's CPLD and FPGA families. What is an EPLD? An Erasable Programmable Logic Device is a non-volatile programmable logic IC that uses EPROM/EEPROM storage cells to retain configuration after power-down. In the system hierarchy, EPLDs sit between discrete TTL/CMOS glue logic and modern FPGAs: they replace multiple 74-series logic packages with one re-programmable device, are slower and lower density than CPLDs/FPGAs, but offer deterministic timing and instant-on behavior. The EP910 was one of the earliest commercially successful EPLDs. The EP910LC-35 integrates 24 macrocells, each combining a programmable AND/OR array with an output register, and supports toggle rates up to 28.6 MHz at the 35ns speed grade. It is built on a CMOS EPROM process, allowing windowed (ceramic) or one-time-programmable plastic package versions to be erased via UV light. I/O pins feature programmable macrocell flip-flops with individual output enable control. The architecture follows the classic sum-of-products PLA structure: a programmable AND plane feeds a fixed OR plane, with each macrocell containing a foldback path for implementing D, T, JK, or SR flip-flop functions. Pin-to-pin delay is uniform across all paths, simplifying timing closure compared to early FPGAs. Typical applications include glue logic replacement in industrial controllers, address decoding for legacy 8/16-bit microprocessor buses (8086, 68k, Z80), bus arbitration, state-machine controllers, and educational CPLD prototyping. It was widely designed into telecommunications, military, and aerospace systems in the late 1980s and 1990s. When designing with this device, verify timing closure against the 35ns worst-case propagation delay at 5V, ensure adequate decoupling on VCC, and use a programmer such as the Altera Logic Programmer or compatible third-party tools. Modern designs are strongly encouraged to migrate to MAX II/MAX V CPLDs for cost, density, and active lifecycle support. This page synthesizes Rochester Electronics authorized-stock data, Altera legacy datasheet parameters, drop-in alternatives from the same EP910 Classic family, and practical design guidance not found in any single distributor listing.
EP910LC-35H - 24-Macrocell Classic EPLD, 35ns | Altera DIP-40
The Altera EP910LC-35H is a high-performance Classic EPLD from the EP910 family, featuring a 24-macrocell architecture housed in a 40-pin Ceramic DIP (J-Lead) package. It belongs to Altera's Classic EPLD family, which provides erasable programmable logic with 450 usable gates, 24 macrocells, and propagation delays of approximately 35 ns at commercial temperature grade. The 'LC' suffix indicates low-power CMOS technology and 'H' indicates the ceramic DIP package variant. A Classic EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic device that preceded modern CPLDs and FPGAs. Architecturally, an EPLD consists of an AND/OR logic array feeding a fixed number of macrocells, each containing a flip-flop and configurable output. Compared to a discrete TTL/CMOS logic implementation, an EPLD integrates equivalent gate counts (here ~450 gates) into a single reprogrammable IC, while compared to an FPGA, an EPLD offers non-volatile configuration (UV-erasable EPROM technology in this part) and deterministic, predictable timing that does not require external boot memory. The EP910 sits in the system hierarchy as: programmable logic -> EPLD/CPLD -> digital logic IC -> semiconductor. Key features include 24 macrocells, 36 user I/O pins, 10 dedicated inputs, a maximum propagation delay of 35 ns (tpd), and 5V CMOS operation. The EP910LC-35H also supports in-system UV erasure and reprogramming, has a maximum toggle frequency in the tens of MHz range, and is built on a low-power CMOS process that is compatible with TTL logic levels on its I/O pins. The device is suitable for legacy glue-logic and bus-interface designs. Architecturally, the EP910LC-35H uses a sum-of-products (AND-OR) PLA feeding a 24-macrocell register array, with a programmable interconnect that links each macrocell to one of 36 I/O pins. The 'LC' designation indicates the device is built on Altera's 0.8-micron CMOS EPROM process with low quiescent current (typically under 100 mA ICC). Programming is performed via a standard Altera programming algorithm on a hardware programmer; erasure requires approximately 20 minutes of UV exposure through the ceramic window (note: 'H' = ceramic DIP package with quartz window). Typical applications include legacy industrial controllers, 5V TTL bus-interface glue logic, military and aerospace systems (per /883 screening on related variants), vintage computing peripherals, and replacement of discrete 74LS TTL logic in board-level redesigns. The EP910LC-35H is also commonly used in retrocomputing projects and as a teaching vehicle in digital logic courses. When designing with this device, note that the EP910LC-35H is a legacy 5V part: ensure 4.75V-5.25V VCC, place a 0.1uF decoupling capacitor near each VCC pin, and avoid modern 3.3V logic interfaces without level shifters. The ceramic DIP package requires a socket for UV erasure programming. For new designs, consider modern MAX II or MAX V CPLDs which offer lower power, smaller packages, and in-system programmability. This page synthesizes distributor pricing (Rochester Electronics, LCSC, Jotrin, Censtry), drop-in alternatives within the Altera EP910 family, and practical design notes not consolidated in the manufacturer datasheet.
EP910LC-35T - 24-Macrocell 35ns CMOS Classic EPLD | Altera
The Altera EP910LC-35T is a member of the Classic EPLD (Erasable Programmable Logic Device) family fabricated on an advanced CMOS process, delivering 450 usable gates and 24 macrocells with a 35ns pin-to-pin propagation delay in a 44-pin PLCC package. Designed for high-speed, low-power logic integration, this part operates from a single 5V supply and is packaged in a J-lead surface-mount PLCC outline suitable for socketed or soldered production assemblies. A Classic EPLD is a non-volatile, UV-erasable programmable logic device positioned historically between simple PAL/GAL devices and modern CPLDs/FPGAs. In the system hierarchy, EPLDs belong to the programmable logic family, sitting above discrete logic ICs and below today's high-density FPGAs. They are typically used for glue logic, address decoding, state machines, and bus interfacing in 5V legacy designs where deterministic pin-to-pin timing is required. Key features of the EP910LC-35T include 24 macrocells arranged in logic blocks, 36 user I/O pins, in-system programmability via the Altera EPROM-based architecture, and a 28.6MHz maximum operating frequency. The device consumes CMOS-level standby current, supports JTAG-compatible boundary-scan testing on selected package variants, and provides tri-state output control on every macrocell for bus-oriented applications. The EP910LC-35T utilizes Altera's Classic architecture combining a global interconnect with local macrocell feedback, allowing each macrocell to implement combinatorial or registered logic with configurable output polarity. The 35ns speed grade reflects the tPD (pin-to-pin delay) at 5V VCC, which is adequate for peripheral decode and slow-state-machine use cases rather than high-speed datapath logic. Typical applications include 5V address decoding in legacy microprocessor boards, glue-logic replacement of discrete 74LS/74HC gates, bus-interfacing adapters between 8-bit and 16-bit peripherals, and replacement of multiple PAL/GAL devices on industrial control boards. The PLCC-44 footprint also makes it a popular choice for socketed field-replacement scenarios. When designing with this device, ensure the design fits within 24 macrocells and uses the supplied Altera MAX+PLUS II development tools (legacy) for fitting, simulation, and programming file generation. Note that Classic EPLDs are mature/OEM-only devices; current production is limited to authorized distributors stocking legacy inventory. This page synthesizes distributor pricing, legacy cross-references, package-compatible alternatives, and practical design notes for engineers maintaining or replacing EP910-series devices in long-lifecycle equipment.
EP910LC-40 - 450-Gate CMOS EPLD, 40ns, PQCC-44 | Rochester / Altera
The Altera EP910LC-40 (re-stocked by Rochester Electronics) is a 450-gate, 24-macrocell CMOS Erasable Programmable Logic Device (EPLD) from the Altera Classic EPLD family, packaged in a 44-pin Plastic Leaded Chip Carrier (PQCC-44) and specified for a 40ns propagation delay. It operates from a single 5V supply, is housed in a windowless plastic J-lead carrier, and is a member of the EP910 family that succeeded the EP610 and EP900 series as Altera's mainstream 5V CMOS EPLDs in the late 1980s and 1990s. An EPLD (Erasable Programmable Logic Device) is a type of non-volatile programmable logic that combines multiple PAL/GAL-like macrocell blocks on a single CMOS die. EPLDs sit in the hierarchy below modern CPLDs and FPGAs: macrocell -> PLD -> EPLD -> CPLD -> FPGA -> programmable logic -> semiconductor. Compared with bipolar PALs, EPLDs deliver lower power (CMOS), higher density (24 macrocells versus 8-16 in early PALs), and reprogrammability using either UV-erasable EPROM cells (windowed ceramic packages) or one-time-programmable EPROM cells (windowless plastic packages). Key features of the EP910LC-40 include 450 usable gates, 24 macrocells distributed across two logic blocks, a 40ns worst-case pin-to-pin propagation delay (tPD) at 5V, 25 MHz maximum toggle frequency, 36 user I/O pins, and 4 dedicated inputs. Architecture is a sum-of-products AND/OR array driving 24 D-type flip-flops with individual preset/reset, J-lead PQCC-44 surface-mount package, 5V single-supply operation, and CMOS power consumption typically under 200 mW. A pin-compatible industrial-temperature grade EP910LI-40 also exists for -40C to +85C deployments. The EP910 architecture combines a global interconnect with two Logic Array Blocks (LABs), each containing 12 macrocells fed by a programmable AND array. Configuration is stored in on-chip EPROM cells, so the device retains its pattern through power cycles without external boot memory - a key advantage over SRAM-based FPGAs of the era. Programming is performed using an Altera Logic Programmer (e.g., PLAD-J, PLAD-32) via the JTAG-like 4-wire serial interface, and the pattern can be erased with UV light through a quartz window (ceramic variants) or locked with security bit in windowless plastic variants. Typical applications for the EP910LC-40 include industrial control glue logic, address decoding for microprocessor and DSP buses, peripheral interface adaptation, vintage PC chipset replacement (e.g., ISA bus glue logic, DMA controller state machines), retro computing and arcade board repair, telecom backplane glue logic, and legacy test equipment. Its 36 I/O pins and 24 flip-flops are well matched to bus-controller state machines and small synchronous interfaces where a few PALs would otherwise be required. When designing with this device, note that 5V CMOS input thresholds are not 3.3V-tolerant - level shifting is required to interface with modern 3.3V logic. The PQCC-44 J-lead footprint needs a socket or careful reflow profile; the package is not pin-compatible with PLCC-44 sockets unless a J-to-PCB adaptor is used. Use the Altera MAX+PLUS II or classic A+PLUS design software for schematics, synthesis and programming file generation; modern toolchains can target EP910 via third-party synthesis flows.
EP910LC-40H - 40ns Classic EPLD, 24 Macro Cells | Altera
The Altera EP910LC-40H is a member of the Classic EPLD (Erasable Programmable Logic Device) family, a high-speed, low-power CMOS programmable logic IC delivering 24 macro cells and 450 usable gates in a through-hole ceramic DIP package. The "-40" speed grade indicates a 40 ns maximum propagation delay (tPD), while the "LC" suffix denotes a low-power, low-cost variant and the "H" marking indicates a specific ceramic package option. It operates from a single 5 V supply and is built on UV-erasable CMOS technology that allows multiple design iterations during prototyping. What is a Classic EPLD? An EPLD is an Erasable Programmable Logic Device, a category that sits between simple PAL/GAL devices and modern CPLDs/FPGAs in the programmable logic taxonomy. EPLDs are non-volatile, contain a fixed AND/OR logic array with user-programmable interconnect, and were widely used in the 1980s and 1990s for glue logic, address decoding, state machines, and bus interface functions. The Classic family was Altera's flagship EPLD line before being superseded by MAX series CPLDs. Understanding this lineage helps engineers recognize the EP910 as an early-era programmable logic building block rather than a contemporary FPGA. Key features of the EP910LC-40H include 24 macro cells, 450 system gates, 40 ns pin-to-pin propagation delay (tPD), 5 V single-supply operation (VCC = 4.75 V to 5.25 V), low-power CMOS technology with typical ICC below 100 mA, and UV-erasable EPROM-based configuration. The device is packaged in a 40-pin ceramic DIP (JEDEC CDIP-40) suitable for prototyping, military, and high-reliability applications through-hole assembly. The "LC" (low-power, low-cost) variants consume less current than the original EP910, making them suitable for portable or power-sensitive systems. Typical applications include address decoding for microprocessor systems, bus arbitration glue logic, state machines and sequencers, peripheral interface controllers (e.g., custom UART, parallel I/O), and replacement of discrete TTL/CMOS logic in legacy industrial, military, and aerospace systems. The Classic EPLD architecture is well-suited to wide combinational decoding and registered logic functions, replacing multiple 74LS/74HC packages with a single programmable device. When designing with this part, engineers should note that it is a UV-erasable device requiring a quartz-windowed package for erasure, with an endurance of approximately 100 erase/program cycles. Modern design flows use the MAX+PLUS II or Quartus II Classic device support, or migrate new designs to MAX II/MAX V CPLDs with pin-compatible footprints. This page synthesizes distributor pricing, drop-in alternatives, and practical sourcing notes not found in the standalone manufacturer datasheet.
EP910LC-40T - Classic EPLD, 24 Macrocells, 40ns, PLCC-44 | Altera
The Altera (Intel Programmable Solutions Group) EP910LC-40T is a member of the Altera Classic EPLD family, an erasable programmable logic device fabricated on advanced CMOS technology. It integrates 450 equivalent gates with 24 macrocells and 36 user I/O pins, operates from a single 5V supply, and is offered in a 44-pin Plastic Leaded Chip Carrier (PLCC) package. The -40 speed grade denotes a 40 ns pin-to-pin logic delay (tPD), and the T suffix indicates a tape-and-reel packing option. It is a through-hole or surface-mount device depending on socket choice, widely used for glue-logic integration in legacy industrial systems. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines the architecture of PAL/GAL with on-chip EEPROM or EPROM storage. Within the broader programmable logic hierarchy, CPLDs sit alongside FPGAs (Field-Programmable Gate Arrays) and SPLDs (Simple PLDs), with CPLDs typically offering faster deterministic pin-to-pin timing, lower power consumption, and instant-on behavior versus SRAM-based FPGAs that require a configuration bitstream. CPLDs are widely used for I/O expansion, bus interfacing, address decoding, and state-machine implementation in industrial, telecom, and military systems where deterministic timing is critical. Key features of the EP910LC-40T include 24 macrocells organized into four Logic Expandable AND-OR arrays, 36 dedicated I/O pins, a 40 ns maximum propagation delay (tPD), 25 MHz typical fMAX, and an erase/rewrite endurance of 100 cycles (windowed UV-erase device). The device is programmed using the Altera MAX+PLUS II or earlier APLUS development tools via a dedicated programming hardware interface. The architecture uses a programmable AND-OR array driving macrocell flip-flops with programmable output polarity. Each macrocell provides D, T, JK, or SR flip-flop modes with a dedicated product-term clock and asynchronous clear, giving the device deterministic timing suitable for replacing multiple discrete 22V10/16V8-style PALs. Typical applications include bus-interface glue logic for legacy 8086/Motorola 68k microprocessor systems, address decoding and chip-select generation, industrial control state machines, and replacement of multiple discrete TTL/CMOS logic gates. The wide supply tolerance and CMOS process make it well suited to noisy industrial environments. When designing with this part, note that it is a UV-erasable windowed device (no -J ceramic-window variant noted in this -LC family code, but the EP910 family includes windowed parts). Designers should verify programming socket compatibility and consider modern MAX II/MAX V CPLDs for new designs. This page synthesizes distributor availability, drop-in alternative MPNs from the same EP910 family, and practical design notes not found in the manufacturer datasheet alone.
EP910LC30T - 24-Macrocell Classic EPLD, 30ns, PLCC-44 | Intel
The Intel (formerly Altera) EP910LC30T is a 24-macrocell Classic-family Erasable Programmable Logic Device (EPLD) housed in a 44-pin PLCC package and rated for a 30 ns propagation delay. It belongs to the Altera Classic EPLD family fabricated on advanced CMOS technology and offers approximately 450 usable gates of low-power, high-speed logic integration in a single package. An EPLD (Erasable Programmable Logic Device) is a type of programmable logic IC that combines the non-volatility of EPROM-based configuration with combinational and registered logic blocks. Within the broader IC hierarchy, an EPLD sits below modern FPGAs and CPLDs in density but above simple PAL/GAL devices, providing deterministic pin-to-pin timing useful for glue logic, address decoding, and state-machine replacement. The EP910 is one of the longest-lived members of the Classic family, originally introduced by Altera in the late 1980s and now supported in long-term supply by Rochester Electronics. Key features include 24 macrocells, 450 equivalent gates, 33.3 MHz maximum operating frequency, 30 ns pin-to-pin propagation delay (commercial grade), 5 V CMOS supply, and erasable windowed UV-erase reprogrammability. The LC suffix indicates a low-power CMOS process variant, while the T suffix indicates Tape and Reel packaging. Pin counts include dedicated inputs, I/O pins, and global clock pins arranged around a central AND-OR programmable interconnect. Technically, the EP910 architecture centers on a programmable AND array feeding a fixed OR array, with each macrocell containing a configurable flip-flop, feedback path, and output enable. This architecture yields predictable, deterministic timing that simplifies timing closure compared with newer SRAM-based FPGA fabrics. The device is in-system programmable via the Altera programming algorithm and supports the industry-standard JTAG-style boundary-scan test. Typical applications include bus-interface glue logic, address decoding for legacy 80xx microprocessors, state-machine replacement, peripheral control logic, and industrial controller boards where 5 V-tolerant CMOS logic and deterministic timing are required. The 44-pin PLCC package suits both through-hole socket and surface-mount assembly. When designing with the EP910LC30T, plan for a single 5 V rail, a programming header compatible with the Altera ByteBlaster or equivalent, and proper decoupling of VCC pins. Note that newer Altera/Intel MAX-series CPLDs are recommended for new designs; the EP910 family is intended for legacy support and long-lifecycle maintenance.
EP910LC44 - Classic EPLD, 24 Macrocells, 44-Pin PLCC | Intel / Altera
The Intel / Altera EP910LC44 is a 24-macrocell Classic EPLD from Altera's industry-defining Erasable Programmable Logic Device family, fabricated on advanced CMOS technology and housed in a 44-pin PLCC (J-leaded) package. The Classic architecture integrates up to 24 macrocells with 240 product terms and a programmable AND/OR array, providing a high-speed, low-power replacement for discrete TTL/CMOS glue logic on legacy boards. A Classic EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic device that sits in the historical hierarchy between simple PAL/GAL devices and modern FPGAs/CPLDs. Classic EPLDs use EPROM or EEPROM cells to store the AND/OR fuse matrix and offer one-time or reprogrammable logic integration with deterministic, pin-locked timing, making them ideal for state machines, address decoding, and bus-interface logic that requires predictable propagation delays. The EP910 family specifically belongs to the second-generation Classic family targeting higher integration with up to 36 inputs and 24 outputs in a single device. Key features of the EP910LC44 include 24 dedicated output macrocells, 12 dedicated inputs and 24 I/O lines (36 inputs total), 240 product terms for combinational logic, two global clock inputs, and propagation delay options down to 33 ns (LC grade). The device operates from a single 4.75 V to 5.25 V supply with low CMOS standby current, and the PLCC-44 footprint has remained a stable package choice for long-lifecycle industrial and military systems. The device is also available in speed grades denoted by a numeric suffix (e.g., -30, -40) where the suffix indicates the maximum propagation delay in nanoseconds under commercial test conditions. The architecture is a sum-of-products AND-OR array with feedback paths from each macrocell, supporting both registered and combinatorial outputs. Macrocells include programmable output polarity, D/T/J-K flip-flop modes, and dedicated clock/enable controls. This deterministic architecture makes the EP910LC44 particularly attractive for asynchronous designs where designers need to verify timing by hand without relying on synthesis-time place-and-route analysis. Typical applications for the EP910LC44 include address decoding and wait-state generation in legacy 80x86 and 68k processor boards, bus-interface logic between microprocessors and peripherals, glue-logic replacement for SSI/MSI TTL packages, state-machine controllers in industrial automation, and legacy industrial/military systems where long-term supply stability is essential. The 5 V CMOS interface is compatible with TTL logic levels, simplifying integration into existing 5 V designs without level shifters. When designing with the EP910LC44, engineers should verify the programming algorithm compatibility with their chosen device programmer (Altera-supported tools include the A+PLUS and MAX+PLUS legacy software flows plus modern retro-support via JTAG with appropriate adapters). The device is windowless (one-time-programmable in windowed ceramic variants; plastic PLCC versions are OTP-style or EPROM-based depending on lot). System designers should also confirm pinout compatibility when migrating to other 910-series speed grades, since pin assignments remain constant across the family. This page synthesizes the Altera EP910 family datasheet, distributor availability, and practical design notes into a single decision-ready reference - information not available from any single distributor page.
EP910LC44-30T - 24-Macrocell CMOS EPLD, 33ns, PQCC-44 | Altera
The Altera EP910LC44-30T is a 33ns propagation-delay, PAL-type CMOS Erasable Programmable Logic Device (EPLD) from the Classic EPLD family, packaged in a 44-pin Plastic Leaded Chip Carrier (PQCC-44) with J-bend terminals. It integrates 24 macrocells and offers 240 product terms, providing a flexible logic-integration solution for glue-logic, bus decoding, and state-machine applications in 5V systems. A CMOS Erasable Programmable Logic Device (EPLD) is a non-volatile programmable logic IC that combines the architectural simplicity of PAL-type logic arrays with erasable programming. EPLDs sit in the programmable logic hierarchy between simple PAL/GAL devices and modern CPLDs/FPGAs: EPLD -> PLD -> programmable logic -> logic IC -> semiconductor. They retain the programming on-chip even when powered down, which makes them useful for bootstrap configuration and legacy system replacement. Key features include 12 dedicated inputs, 24 bidirectional I/O lines, and 2 external clock inputs that drive internal registers. The device supports a nominal 5V supply (4.75V to 5.25V) and offers 33ns pin-to-pin propagation delay (tPD) suitable for bus-interface and address-decoding tasks. It is built on advanced CMOS technology for low static power consumption and includes a programmable security bit to protect user logic from unauthorized readback. The PQCC-44 J-lead surface-mount package provides robust mechanical attachment and is rated for the commercial temperature grade. The EP910LC44-30T uses a sum-of-products macrocell architecture: each macrocell contains a programmable AND array feeding an OR gate with a configurable flip-flop, allowing combinational or registered output. The 240 product terms feed the 24 macrocells via a global interconnect, and the device supports asynchronous clear, synchronous preset, and output enable control. Together with the erasable windowed package option in the family, this architecture enables iterative design and field reprogramming. Typical applications include TTL/CMOS logic replacement, random-logic consolidation, address decoding for memory and peripheral buses, bus-multiplexing glue logic, and state-machine implementation in industrial control, telecom, and instrumentation equipment. The 33ns tPD also supports fairly high-speed control-plane paths in legacy 5V designs. When designing with this device, observe the 5V supply tolerance (4.75V to 5.25V) and add a 0.1uF decoupling capacitor close to each VCC pin to suppress switching transients on the parallel macrocell outputs. This page synthesizes distributor pricing, drop-in Altera/Intel Classic EPLD family alternatives, and practical design notes not found in the manufacturer datasheet alone.
EP910LC44-35 - 24-Macrocell EPLD, 35ns, PLCC-44 | Altera Classic
The Altera (now Intel) EP910LC44-35 is a 24-macrocell CMOS Erasable Programmable Logic Device (EPLD) from the Classic EPLD family, housed in a 44-pin PLCC package. It provides 450 usable gates, 36 inputs, 24 I/O lines, and a worst-case propagation delay of 35 ns, with a maximum toggle frequency of 28.6 MHz on the device. What is an EPLD? An EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic device that uses floating-gate memory cells to store the AND/OR array configuration. EPLDs sit in the programmable logic hierarchy between simple PAL/GAL devices (small, one-time-programmable) and complex CPLDs/FPGAs (large, SRAM-based, requiring external boot memory). The EP910 family belongs to the OT (Output) sub-family, which features a PAL-type AND/OR architecture and is fabricated on advanced CMOS technology for high speed and low power consumption. Key features include 24 macrocells with configurable D/T/JK flip-flops, 2 global clock inputs with synchronous/asynchronous clocking options, programmable output enable per macrocell, and a JTAG-compatible in-system programmability interface on selected variants. The device operates from a single 5 V supply with low standby current and is windowed-ceramic (JEDEC standard UV-erasable), allowing re-programmability for prototyping. The EP910 architecture uses a single AND array feeding a fixed OR array, which simplifies timing analysis compared to CPLDs. All 24 macrocells share two global clock pins, and the device supports both combinatorial and registered outputs. The 35 ns speed grade makes it suitable for control logic, glue logic, and address decoding in systems where deterministic pin-to-pin timing is required. Typical applications include bus interface and address decoding in 8086/68000-based systems, state-machine controllers, peripheral glue logic, board-level control registers, and legacy industrial control retrofits. The 5 V supply and TTL-compatible I/O also make it a popular replacement for discrete 74LS logic clusters in older designs. When designing with this part, note that the 35 ns pin-to-pin delay imposes a ceiling on system clock frequency when used in synchronous logic paths; engineers targeting faster speeds should consider the EP910LC-30 or EP910LC-25 variants. The windowed-ceramic package requires a UV eraser for re-programming, while plastic OTP variants (-PC suffix) are single-programming for production. This page synthesizes distributor pricing, same-package EPLD drop-in alternatives, and practical design notes not found in a single manufacturer datasheet.
EP910LC44-40 - 24-Macrocell Classic EPLD, 44-Pin PLCC | Intel / Altera
The Intel / Altera (formerly Altera Corporation) EP910LC44-40 is a member of the Altera Classic EPLD family, an erasable programmable logic device fabricated on advanced CMOS technology for high-speed, low-power logic integration. The EP910LC44-40 delivers 24 dedicated macrocells, 36 total inputs (12 dedicated inputs plus 24 I/O lines), and 240 product terms distributed across the AND/OR array. The "-40" speed suffix indicates a 40 ns pin-to-pin propagation delay (tPD) commercial timing grade, packaged in a 44-pin Plastic Leaded Chip Carrier (PLCC) with the "LC" pinout designation. The "L" prefix denotes low-power CMOS technology, and the device is supported by the legacy Altera MAX+PLUS II / MAX+PLUS development environment using JEDEC-compatible programming files. What is an EPLD? An Erasable Programmable Logic Device (EPLD) is a non-volatile programmable logic IC that uses EPROM/EEPROM storage cells to retain the user's logic configuration. EPLDs sit in the hierarchy: programmable logic -> PLD -> EPLD -> CMOS PLD -> programmable logic device -> semiconductor IC. The Classic EPLD family preceded modern CPLDs in Altera's roadmap, offering a CMOS PAL-type architecture with sum-of-products logic and a fixed AND-to-OR interconnect. EPLDs are typically used for glue logic, address decoding, bus interfacing, state-machine implementation, and peripheral control where deterministic 40 ns timing is acceptable and in-system reprogrammability is not required. Key features of the EP910LC44-40 include 24 macrocells, 240 product terms, 24 bidirectional I/O pins, 12 dedicated input pins, 2 global clock inputs, and TTL-compatible I/O. The device supports 100% TTL-level compatibility and operates from a single 5 V supply. Logic is configured via industry-standard JEDEC maps and may be programmed using Altera's legacy LP6, MP9, or third-party programmers; UV-erasable variants (windowed ceramic DIP/CLCC packages) coexist with one-time-programmable plastic packages in the same family. Architectural enhancements such as programmable macrocell flip-flops and configurable I/O architectures distinguish the Classic family from earlier PAL/GAL devices. Architecturally, the EP910LC44-40 uses a programmable AND array feeding a fixed OR array, with each macrocell containing a flip-flop, output enable, and feedback path. The 2 dedicated clock pins drive the global clock network that fans out to every macrocell flip-flop, while the 24 I/O pins can be individually configured as input, output, or bidirectional. Power consumption is reduced by CMOS technology compared with bipolar PAL parts, and the device operates across the commercial 0C to +70C temperature range. Programming is non-volatile in windowed packages, enabling multiple design iterations via UV erasure. Typical applications include legacy industrial control boards, address decoding for microprocessor/microcontroller systems, peripheral interface glue logic, bus arbitration circuits, and replacement of discrete 74LS/74F TTL logic. Engineers also deploy the EP910 in aerospace and defense sustainment programs, medical equipment long-life-cycle boards, and test & measurement instrumentation where original designs must be maintained for 20+ year product support windows. The 44-pin PLCC package is socket-compatible with production programmers and is footprint-compatible with other PLCC-44 EPLDs in the Classic family. When designing with the EP910LC44-40, note that propagation delay of 40 ns may not meet timing budgets in modern 33 MHz or faster microprocessors; verify setup/hold timing against the asynchronous or synchronous interface requirements. The device must be programmed before use with a JEDEC file generated by MAX+PLUS II (legacy) or compatible tools; designs not following the macrocell product-term limits must be recompiled for the target device. The plastic PLCC package is one-time programmable in non-windowed variants, so plan JTAG-free programming flow during manufacturing. This page synthesizes distributor pricing, same-family drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone, giving engineers a single-decision reference for legacy EPLD procurement.
EP910LI-12 - 24-Macrocell Classic EPLD, 12ns PLCC-28 | Altera
The Altera EP910LI-12 is a member of the Altera Classic EPLD (Erasable Programmable Logic Device) family, integrating 24 macrocells and 450 usable gates on a 1.0-micron CMOS EPROM process. Housed in a 28-pin PLCC windowed ceramic package with a 12 ns pin-to-pin propagation delay, it is intended for high-speed, low-power logic integration in glue-logic, bus arbitration, and state-machine roles. The 'LI' suffix denotes the PLCC windowed package and the 'I' suffix indicates the industrial operating temperature range of -40C to +85C, while '-12' marks the speed grade. Background: an EPLD (Erasable Programmable Logic Device) is a type of programmable logic IC that sits between simple SPLDs/CPLDs and high-density FPGAs. EPLDs use EPROM, EEPROM, or flash cells to retain configuration, combine AND/OR arrays with output macrocells, and historically delivered fast deterministic propagation delays in the 5-15 ns range. The EP910 belongs to the Classic EPLD family hierarchy: EPLD > programmable logic > PLD > digital IC > semiconductor. Classic EPLDs were widely deployed in the 1990s for glue logic, address decoding, and peripheral interfacing where speed and simplicity outweighed gate count. Key features of the EP910LI-12 include 24 macrocells, 36 inputs (with input registers), 24 I/O pins, 76.9 MHz maximum operating frequency, and 12 ns worst-case combinatorial propagation delay (tPD). Power consumption is specified at less than 200 mW typical at 5 V, with TTL-compatible I/O and a 5 V VCC supply. Programming uses the original Altera Master Programming Unit (MPU) or compatible third-party programmers via the dedicated program/erase pins, and the ceramic windowed package enables UV erasure for prototyping and design iteration. Typical applications include 5V bus arbitration, address decoding, peripheral interface glue logic, state machines, and legacy system retrofits. When designing, ensure all inputs are tied to a defined logic level to avoid floating-pin issues, observe the recommended decoupling scheme (one 0.1 uF capacitor per VCC pin), and verify that the chosen programmer supports the Classic EPLD JTAG/byte-blaster protocols before committing to the EP910LI-12. Note that Altera Classic EPLDs are mature EOL components - consult Rochester Electronics for current authorized inventory and lifecycle data. This page synthesizes distributor pricing, drop-in alternatives from the same Classic EPLD family, and practical design notes not found in the original Altera datasheet.
EP910LI-15 - 15 ns Classic EPLD, 36 I/O | Altera | Logic Integration
Altera EP910LI-15 is a high-speed, low-power programmable logic device from the Altera Classic EPLD family, supplied in a 44-terminal J-lead ceramic chip carrier identified as PQCC44. The device operates from a 4.5 V to 5.5 V supply and supports an operating temperature range of -40 °C to +85 °C. It provides 12 dedicated inputs and 24 configurable input/output lines through its macrocell outputs. The “-15” ordering designation corresponds to a 15 ns speed grade in the available search context, while the exact device architecture and timing limits should be confirmed from the manufacturer datasheet before a new design. The EP910LI-15 is a programmable logic IC rather than a fixed-function gate array, combining logic integration with programmable configuration. Its PLD classification places it below general-purpose FPGA devices in flexibility but above discrete combinational logic for applications requiring compact, deterministic implementation of glue logic, state machines, decoders, and interface functions. The 36 available user-signal resources, comprising 12 dedicated inputs and 24 input/output lines, make the device useful for moderately complex board-level control logic. The Classic EPLD architecture is designed to provide predictable logic implementation while reducing the number of separate standard logic packages required on a PCB. CMOS technology supports the low-power logic integration described for the Altera Classic device family. In practice, the EP910LI-15 can consolidate random logic, registered control, and bus-interface functions into one programmable device. The 4.5 V to 5.5 V operating range is appropriate for 5 V logic systems, while the -40 °C to +85 °C range supports industrial-temperature deployments. The PQCC44 ceramic J-lead package is surface-mount technology with a larger ceramic carrier format, so land-pattern verification, mechanical inspection, and process compatibility are important for assembly. For a new production design, confirm the complete pin assignment, configuration procedure, supported design software, timing characteristics, and availability through the manufacturer or an authorized supplier. This page combines verified search facts, pricing and lead-time guidance, package details, and engineering-oriented design considerations for legacy programmable-logic sourcing and board support.
EP910LI-20 - Classic EPLD 24 Macrocells, 20ns | Altera
The Altera EP910LI-20 is a member of the Altera Classic Erasable Programmable Logic Device (EPLD) family, integrating 24 macrocells in a high-speed, low-power CMOS architecture. It provides 16 dedicated input pins, 24 I/O pins, and operates at a tpd (pin-to-pin delay) of 20 ns with a maximum toggle frequency of 62 MHz. The part is supplied in a 40-pin ceramic DIP (Windowed) package, indicated by the 'L' package designator and 'I' industrial temperature grade. An EPLD (Erasable Programmable Logic Device) is a type of programmable logic that combines the non-volatility and reprogrammability of UV-erasable EPROM technology with the macrocell-based logic density of early PLDs. EPLDs sit in the hierarchy: programmable logic -> PLD -> EPLD -> CMOS EPLD -> logic integration IC, predating modern CPLDs and FPGAs. The Classic family was Altera's flagship high-speed, low-power logic integration platform in the late 1980s and 1990s. The EP910LI-20 is fabricated on an advanced CMOS process that delivers low static power consumption typical of the Classic family, typically 200 mA ICC at military/industrial operating conditions. The device is pin-compatible across the EP910 family, allowing designers to swap speed grades (EP910LC-40, EP910LC-35, EP910LC-30) without PCB rework. Each macrocell offers configurable combinatorial or registered logic, with dedicated product-term architecture supporting sum-of-products implementation typical of the Classic era. Typical applications for the EP910LI-20 include state-machine control, address decoding, glue logic replacement, and legacy system maintenance where modern FPGAs are unsuitable for form-factor or environmental reasons. The windowed ceramic DIP package supports field erasure via UV light, enabling iterative development cycles. The industrial temperature grade ('I' suffix) supports operation across -40C to +85C ambient environments. When designing with this EPLD, designers must respect the 5V VCC requirement and the 20 ns propagation delay budget. Power sequencing should ensure clean rise/fall on VCC to avoid latch-up. For new designs, the EP910LC series in plastic DIP packages is recommended; the EP910LI is preferred for long-lifecycle, harsh-environment, or field-reprogrammable applications.
EP910LI-20T - Classic EPLD, 24 Macrocells, 20ns DIP-20 | Altera
The Intel / Altera EP910LI-20T is a member of the Classic EPLD (Erasable Programmable Logic Device) family, delivering 24 macrocells, 10 dedicated inputs, and 20 I/O pins in a 20-pin ceramic DIP (CDIP-20) through-hole package. It is fabricated on an advanced CMOS EPROM technology and offers a 20 ns pin-to-pin propagation delay with a 95 MHz maximum operating frequency, targeting high-speed, low-power logic integration. A Classic EPLD is a one-time or UV-erasable programmable logic device that sits between simple PLAs and modern FPGAs in the programmable-logic hierarchy. The Classic family provides deterministic pin-to-pin timing, non-volatile configuration storage on-chip, and a single +5 V supply requirement, which makes them attractive for legacy glue-logic, bus-interface, and state-machine designs where designers need predictable timing without a separate boot PROM. The EP910 is the highest-density member of the family and is pin-compatible with the lower-density EP610 within the Classic portfolio. Key features of the EP910LI-20T include 24 macrocells organised into four Logic Array Blocks (LABs), 20 bidirectional I/O pins, 10 dedicated input pins, a 20 ns combinatorial propagation delay, and an industry-standard JEDEC-standard programming algorithm that allows third-party programmers to configure the device. The ceramic DIP-20 package with the -20 speed grade is the slowest of the EP910 speed bins (which span -12, -15, and -20), making it suitable for cost-sensitive, lower-speed applications. The part is offered in industrial (-40 C to +85 C) and commercial (0 C to +70 C) operating ranges. Architecturally, the EP910 uses a sum-of-products AND/OR array feeding an expandable macrocell with a configurable flip-flop, XOR gate, and output enable. Its AND array is fully connected across all inputs and feedback terms, giving designers 100% product-term utilisation. The device is programmed with a 21 V programming voltage applied through industry-standard JTAG-like or third-party algorithms, and a windowed ceramic package variant allows UV erasure for prototyping. Typical applications include TTL/CMOS glue logic replacement, address decoding for microprocessor and memory systems, state machines for industrial control, bus-interface adaptation between different logic families, and legacy system maintenance where the original Altera Classic logic must be replicated. The EP910LI-20T is widely stocked in the long-lifecycle and mil-aero markets through distributors such as Rochester Electronics. When designing with the EP910LI-20T, treat the 20 ns propagation delay as a worst-case specification across temperature; derate by 20-30% when designing for the industrial temperature range. The ceramic DIP-20 footprint allows hand-soldering for prototypes, but designers targeting production should consider the plastic DIP-20 (PC-20) variant or migrate to a MAX series device if higher density is required. This page synthesises distributor pricing, drop-in same-family alternatives, and practical design notes not found in the original Altera datasheet, providing a modern procurement reference for engineers maintaining legacy systems built on the Classic EPLD family.
EP910LI-30 - 24-Macrocell EPLD, 30ns, PQCC44 | Rochester/Altera
The Rochester Electronics EP910LI-30 is a 24-macrocell Classic-series Erasable Programmable Logic Device (EPLD) with a 30ns propagation delay, housed in a 44-pin Plastic Leaded Chip Carrier (PQCC44 / PLCC-44) surface-mount package. The EP910 family delivers approximately 450 usable gates and 24 macrocells backed by non-volatile UV-erasable CMOS logic, targeting glue-logic replacement and medium-complexity state-machine integration on legacy +5V digital boards. An EPLD (Erasable Programmable Logic Device) is a type of programmable logic that sits in the design hierarchy between simple PLDs (PAL/GAL) and modern FPGAs/CPLDs. EPLDs use a sum-of-products AND/OR architecture with a programmable interconnect network and can be erased via ultraviolet light and re-programmed, making them ideal for prototyping and field updates. The EP910 occupies the mid-density tier of the Altera Classic family, providing more logic capacity than 22V10-style PALs while consuming far less board area than a discrete TTL/CMOS implementation. Key features of the EP910LI-30 include 24 macrocells, 10 dedicated input pins and 22 I/O pins, 450 equivalent gates, 30ns pin-to-pin propagation delay (tPD), and a 5V ±5% single supply. The 'L' suffix denotes the low-power CMOS process, and the 'I' suffix indicates the industrial operating temperature range of -40C to +85C. The PQCC44 J-leaded package supports standard surface-mount assembly and is socket-compatible with the EP910LC44 (commercial-temperature variant), simplifying qualification across product lines. Architecturally, the EP910 is implemented in 1.0-micron CMOS EPLD technology with EPROM-style programmable interconnect, providing non-volatile configuration retention without external configuration memory. Each macrocell contains a programmable flip-flop, feedback path, and output enable control. The device is programmed via a standard Altera/Altera-compatible programming algorithm and is fully supported by legacy MAX+PLUS II and classic Altera development toolchains. Typical applications include TTL/CMOS glue-logic integration, address decoding for legacy 8-bit and 16-bit microprocessors (8086, 68000, Z80, 8051), bus-interface state machines, peripheral controllers, and replacement of discrete 74LS/74HC logic on industrial control boards. Its 30ns tPD suits buses clocked up to approximately 16 MHz. As of 2026-09-10 the part is supplied exclusively through authorized and aftermarket channels stocking Rochester Electronics inventory, reflecting original Altera EOL of the EP910 family in the late 1990s. When designing with the EP910LI-30, allocate a 1.5 square-inch copper pour beneath the PLCC socket to keep junction temperature within industrial limits, and observe Altera's recommended programming algorithm for in-system or socket programming. Designers should also note that newer MAX II / MAX V CPLDs from Intel (formerly Altera) are NOT pin-compatible with the EP910 footprint. This page synthesizes distributor pricing, Rochester Electronics lifecycle status, drop-in alternatives, and practical design notes not consolidated in the original Altera datasheet.
EP910LI-30T - 24-Macrocell Classic EPLD, 30ns, PQCC-44 | Altera
The Altera EP910LI-30T is a member of the Altera Classic EPLD family, providing 24 macrocells (450 usable gates) of CMOS programmable logic in a 44-pin Plastic Leaded Chip Carrier (PQCC-44) package. The "LI" suffix denotes an industrial temperature range and 30 ns propagation delay (tPD), while the trailing "T" indicates a Tape and Reel packaging option for surface-mount assembly. What is a Classic EPLD? A Classic Erasable Programmable Logic Device (EPLD) is a type of programmable logic IC that combines AND/OR arrays with user-programmable macrocells, enabling the replacement of multiple discrete SSI/MSI logic gates with a single re-programmable device. EPLDs sit at the lower end of the programmable logic hierarchy below CPLDs and FPGAs, offering non-volatile (UV-erasable) configuration, predictable timing, and fast pin-to-pin propagation delays - ideal for glue-logic, state-machine, and bus-Interface applications. The EP910LI-30T delivers 24 macrocells, 10 dedicated input pins, 24 I/O pins (bidirectional), and operates over the industrial temperature range of -40°C to +85°C. It is fabricated on advanced CMOS technology, providing high-speed, low-power logic integration with tPD of 30 ns, tCO of 20 ns, and fMAX compatible with high-speed control logic. The device is housed in a J-leaded PQCC-44 surface-mount package. Architecturally, the EP910 uses a sum-of-products PLA structure feeding registered output macrocells, with each macrocell offering product-term allocation, output polarity control, and a flip-flop. Programming is performed via a standard EPROM programmer using the Altera Logic Programmer or compatible tools. Typical applications include bus-interface glue logic, state-machine replacement of discrete 74LS/74HC logic, address decoding in microprocessor systems, and timing-control circuits in industrial controllers. Designers often choose the EP910 family when non-volatile configuration, deterministic timing, and high I/O count in a small plastic package are required. When designing with this device, note that the PQCC-44 footprint requires socketed or reflow assembly; ensure proper handling of UV-erasable windowed versions if reprogramming is needed. For modern designs, verify that software tools (Altera MAX+PLUS II legacy support) are still accessible in your workflow. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the original Altera datasheet.