FPGA & CPLD
Produits (6666)
EP910LI-35 - Classic EPLD, 24 Macrocells, 38ns PLCC-44 | Altera
The Altera EP910LI-35 is a 24-macrocell member of the Altera Classic EPLD family, delivering 900 usable gates in a 44-pin PLCC package with a 35 ns propagation delay. As an industrial-temperature variant (-40 °C to +85 °C) of the EP910 die, it provides 38 user I/O pins and operates from a single 5 V supply, targeting glue-logic replacement, address decoding, and state-machine consolidation in industrial and legacy systems. A CPLD (Complex Programmable Logic Device) is a non-volatile, electrically erasable programmable logic device that combines the instant-on characteristics of PAL/GAL with macrocell-level logic density. Within the broader taxonomy, the EP910 belongs to the Classic EPLD family (CPLD -> EPLD -> PLD -> programmable logic -> semiconductor), which Altera positioned as the forerunner of modern MAX-series CPLDs. The Classic family targets bus-interface logic, peripheral controllers, and high-speed state machines where low-cost, deterministic logic is required. Key features include a 76.9 MHz maximum counter frequency (f_CNT), 24 macrocells split across two Logic Array Blocks (LABs), a 24-pin input array, and a pin-locking architecture for predictable PCB layout reuse. EPROM-based configuration supports >100 erase/program cycles for prototyping iteration, and the device retains its logic configuration without external memory. The PLCC-44 (J-leaded) package provides surface-mount assembly with mechanical robustness suited to industrial sockets and field-replaceable modules. Architecturally, the EP910 uses sum-of-products logic feeding programmable output macrocells with configurable flip-flop polarity, feedback paths, and tri-state control. Each macrocell can be configured as registered or combinatorial, allowing sequential and combinational logic to be intermixed freely. The 38-ns t_PD reflects the older Classic CMOS process node, sufficient for buses under ~25 MHz but slower than modern MAX V or MAX 10 devices. Typical applications include peripheral glue logic, address decoding for microprocessor systems, bus arbitration, legacy industrial control boards, and retro-computing platforms. The wide supply tolerance (4.75 V to 5.25 V) simplifies integration with TTL/CMOS 5 V logic. Designers also use EP910 for state machines in CNC controllers, test equipment front panels, and aerospace ground-test instrumentation where deterministic timing matters more than raw speed. When designing with this device, observe the 35 ns propagation delay when computing set-up margins for downstream registers. The PLCC-44 footprint differs from modern 0.5 mm-pitch QFNs, so PCBs targeting EP910 family variants should accommodate the 1.27 mm J-lead pitch. Use Rochester Electronics as the authorized continuing source for end-of-life inventory. This page synthesizes distributor pricing, drop-in pin-compatible Classic-family alternatives, package diagrams, and PCB-layout guidance not consolidated in any single distributor catalog page.
EP910LI-35BF - 24-Macrocell Classic EPLD, 35ns, PLCC-44 | Altera
The Altera EP910LI-35BF is a member of the Altera Classic Erasable Programmable Logic Device (EPLD) family, delivering 24 macrocells and 450 usable gates in a 44-pin PLCC (Plastic Leaded Chip Carrier) package with industrial-grade speed grade tpd=35ns. It is fabricated on advanced CMOS technology and provides 100% TTL emulation with pin-to-pin compatibility across the EP910 family. The "LI" suffix indicates the PLCC package and industrial operating temperature range. An EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic IC that sits between simple PAL/GAL devices and complex FPGAs in the programmable logic hierarchy (PAL/GAL -> EPLD -> CPLD -> FPGA -> SoC FPGA). It offers erasable/reprogrammable combinational and registered logic, suitable for glue-logic, address decoding, state machines, and bus-interface functions that previously required multiple discrete SSI/MSI TTL parts. EPLDs are characterized by deterministic pin-to-pin timing, a macrocell-based architecture, and predictable routing delays, which is critical for asynchronous and memory-interface designs. Key features of the EP910LI-35BF include 24 macrocells, 450 usable gates, a maximum pin-to-pin propagation delay (tpd) of 35 ns, a maximum toggle frequency (fmax) of 28.6 MHz, and a 5V supply. The device supports in-system UV-erase (windowed) operation and is packaged in a 44-pin PLCC (J-lead) carrier. Compared with bipolar PAL/GAL devices, the CMOS EP910 offers substantially lower power dissipation, while providing higher integration for logic consolidation. Internally, the EP910LI-35BF uses a macrocell-based AND/OR array architecture: each macrocell contains a programmable AND-term array, an XOR gate for polarity control, and a flip-flop (D/T/JK/SR selectable). Output enable and feedback are fully programmable, and unused macrocells can be disabled to reduce quiescent current. The device is programmed via a standard EPROM/UV-erase programmer with a 20-pin programming algorithm compatible with the Altera Classic family. Typical applications include address decoding for 8/16-bit microprocessors and DMA controllers, glue-logic replacement for TTL/CMOS discrete gates, register/latch/FSM consolidation in industrial controllers, bus-interface adapters (e.g., legacy peripheral bus glue), and prototyping platforms where erasability is needed. Because of its 5V supply and TTL compatibility, the EP910 is also used to retrofit older designs that must remain 5V throughout the signal path. When designing with the EP910LI-35BF, ensure the device is decoded cleanly from other PLDs or memory maps to avoid bus contention, use a 0.1uF decoupling capacitor close to each VCC pin, and respect the IOL/IOH DC specifications (typically 4-8 mA per output) to avoid exceeding drive strength when interfacing to heavily loaded buses. This page synthesizes distributor pricing, drop-in alternatives, application guidance, and practical design notes not found in the standalone Altera datasheet, including a side-by-side comparison with sibling Classic EP910 speed grades and package options.
EP910LI-35H - 900 Gates, 24-Macrocell Classic EPLD, 35ns PLCC-44
The Intel / Altera EP910LI-35H is a 900-gate, 24-macrocell member of the Altera Classic Erasable Programmable Logic Device (EPLD) family, fabricated in advanced CMOS technology and packaged in a 44-pin PLCC (J-lead) housing. The “-35” speed grade corresponds to a tPD of 35 ns, while the “H” suffix denotes the lead-free / industrial operating temperature option within the Classic EPLD roadmap. The part integrates 24 macrocells and approximately 900 usable gates of combinational and registered logic, supported by a programmable interconnect array (PIA), global and product-term clock networks, and a non-volatile EPROM cell that retains the user pattern with UV-erase reprogrammability. An EPLD (Erasable Programmable Logic Device) is a class of one-time- or erasable-programmable CMOS logic that historically preceded modern flash-based CPLDs and FPGAs. Within the programmable logic hierarchy, EPLDs sit above discrete 22V10-style PALs (in density and macrocell richness) but below contemporary non-volatile CPLDs and SRAM-based FPGAs in raw logic capacity, I/O count, and I/O standards support. The Classic EPLD family was Altera’s flagship low-power, high-speed glue-logic platform in the 1980s and 1990s, optimized for bus arbitration, address decoding, state-machine control, and peripheral interfacing on 5 V digital boards. Key features of the EP910LI-35H include 24 dedicated macrocells with configurable D/T/JK flip-flop behavior, a programmable AND/OR array with 36 inputs feeding the PIA, pin-compatible speed grades (tPD 12 to 40 ns) that allow easy in-family upgrades/downgrades, low CMOS standby current suitable for battery-backed systems, and JEDEC-standard programmer compatibility. The architecture separates input macrocells (with registers) from output macrocells (with feedback), enabling efficient bi-directional bus implementation without external transceivers. Typical applications include 5 V microprocessor glue logic (address decoding, wait-state insertion, interrupt prioritization), peripheral interface controllers (PIO, UART glue, custom IEEE-488 / GPIB state machines), industrial control sequencers, military and avionics legacy systems requiring MIL-STD-883 processing, and replacement designs for end-of-life discrete SSI/MSI logic. Because the part is widely second-sourced (Rochester Electronics, etc.) it remains attractive for long-lifecycle programs. Designers should note the EP910LI-35H is a mature, NRND/EOL part on most franchised distributor line cards; long-term programs typically procure through authorized aftermarket channels. Verify pinout (44-pin PLCC) and speed grade against the original datasheet before substituting with other -35 or -30 speed grades. This page synthesizes distributor pricing, in-family and cross-family drop-in alternatives, and practical design notes not consolidated on the manufacturer datasheet alone.
EP910LI-35T - 24-Macrocell Classic EPLD 35ns 44-PLCC | Intel
The Intel (formerly Altera) EP910LI-35T is a 24-macrocell Classic EPLD from the EP910 family, fabricated on advanced CMOS technology and offered in a 44-pin PLCC package with 35 ns pin-to-pin propagation delay. It delivers 450 usable gates, 24 macrocells, and a maximum toggle frequency of 28.6 MHz, all from a single 5 V supply. An EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic IC historically used as a glue-logic replacement for multiple TTL/CMOS SSI/MSI parts. Sitting in the taxonomy between PAL/GAL and modern CPLD/FPGA, EPLDs offer deterministic combinational and registered logic with EPROM- or EEPROM-based configuration. The EP910 family from Intel/Altera represents one of the industry-standard Classic EPLD lines used in long-life-cycle industrial, military, and aerospace systems. Key features include 24 macrocells with configurable I/O architecture, 450 usable gates, 35 ns tPD propagation delay, 28.6 MHz fMAX toggle frequency, and a single 5 V (4.75 V–5.25 V) supply. The device supports in-system programmability via Altera's classic programming algorithm and offers 10-year data retention thanks to EPROM-based configuration cells. The 44-pin PLCC package is JEDEC-standard and supports both socketed and surface-mount assembly. The EP910LI-35T architecture combines a global interconnect matrix with per-macrocell product-term arrays, allowing wide AND-OR logic and buried register feedback. Compared with discrete TTL/MSI replacement, it reduces board area by typically 5:1 to 10:1 while improving timing predictability and reducing power consumption to CMOS levels at idle. Typical applications include industrial control glue logic, military/aerospace retrofit boards, telecom interface adapters, and legacy peripheral controllers. The wide supply tolerance (4.75 V–5.25 V) makes it tolerant of legacy 5 V backplanes. The deterministic 35 ns delay simplifies worst-case timing closure in asynchronous control paths. Designers should note that the EP910 family is in long-term support status - new designs are not recommended, but Obsolescence/EOL notifications typically allow multi-year last-time-buy windows via franchised distributors and aftermarket suppliers like Rochester Electronics. Programming requires Altera-supported hardware (e.g., Altera Logic Programmer or compatible). This page synthesizes verified distributor pricing, drop-in replacement options (including the EP910LC and EP910ILC family variants), and practical design considerations not consolidated in the original datasheet.
EP910LI-35Y - Classic EPLD 450 Gates 24 Macrocells 35ns | Altera/Intel
The Intel (formerly Altera) EP910LI-35Y is a member of the Altera Classic EPLD (Erasable Programmable Logic Device) family, fabricated on advanced CMOS technology to deliver high-speed, low-power logic integration in a 44-pin PLCC package. It integrates 450 usable gates and 24 macrocells with a worst-case propagation delay of 35 ns, making it one of the slowest (and therefore lowest-power) speed grades in the EP910 family. The device is offered in the industrial temperature range (the "I" suffix) and operates from a single 5 V supply. The "Y" suffix denotes a RoHS-compliant lead-free finish, while "L" identifies the low-power CMOS process option, and "35" indicates the 35 ns tpd speed grade. Architecture-wise, the EP910LI-35Y provides a programmable AND/OR array with shared logic expanders, a programmable macrocell flip-flop, and configurable output polarity, allowing designers to implement combinational and registered logic functions. The Altera Classic family is an early-generation programmable logic architecture that preceded the modern MAX series, designed for glue-logic, bus decoding, and state-machine replacement on 5 V systems. An EPLD (Erasable Programmable Logic Device) is a type of programmable logic IC that combines PAL-like AND/OR arrays with reprogrammable macrocells, offering a higher gate density than bipolar PALs while retaining non-volatile configuration. EPLDs belong to the broader hierarchy: programmable logic device (PLD) -> EPLD -> CMOS PLD -> Erasable PLD, sitting between simple PAL/GAL devices and modern CPLDs/FPGAs. Unlike SRAM-based FPGAs, Classic EPLDs retain their configuration in non-volatile memory and power up instantly to a known state, which simplifies system design in industrial controllers. Key features of the EP910LI-35Y include 24 macrocells (each with a flip-flop and I/O pin), 36 dedicated inputs, an internal feedback path that allows buried macrocell registers, and a programmable clock network. The device supports multiple I/O standards on its 24 I/O pins and includes a global clock input. The 44-pin PLCC (J-lead) package provides socket-friendly field upgrades, while the "I" industrial temperature grade covers -40 °C to +85 °C operation. The "Y" lead-free finish makes the part suitable for modern RoHS-compliant assemblies, although the underlying EP910 die is a mature 1980s-1990s architecture. Typical applications include 5 V glue logic replacement (decoders, multiplexers, comparators), address decoding in legacy microprocessor and microcontroller systems, industrial PLC interface logic, state-machine replacement in motor-control and instrumentation, and pin-compatible modernization of EP910-based designs where 35 ns timing is acceptable. The low-power "L" process makes the part attractive for power-sensitive systems that do not require higher speed grades (e.g., EP910LC-25 or EP910DC-25). When designing with the EP910LI-35Y, ensure that all inputs are properly terminated to avoid floating CMOS inputs and that the 5 V supply is well-decoupled with 0.1 µF ceramic capacitors close to VCC pins. Because the device is one of the older Classic EPLDs, programming is performed via legacy Altera programming hardware (e.g., the Altera Logic Programmer or compatible third-party tools) and the AHDL/ABEL hardware description languages that were current at the time of introduction. This page synthesizes distributor pricing, drop-in same-package alternatives from the EP910/EP610 family, and practical design notes not found in the original Altera datasheet.
EP910LI-40 - 24 Macrocell CMOS EPLD, 40ns | Altera | PLCC-44
The Altera EP910LI-40 is a 24-macrocell Classic-series Erasable Programmable Logic Device (EPLD) fabricated on advanced CMOS technology and offered in a 44-pin PLCC package with a 40 ns propagation delay. The 'L' suffix denotes a low-power CMOS process variant, while the 'I' indicates the industrial operating temperature grade, making this device suitable for commercial and industrial control applications where power efficiency and -40C to +85C thermal tolerance are required. An EPLD (Erasable Programmable Logic Device) is a type of programmable logic IC that combines PAL-type AND-OR array logic with a programmable macrocell output stage. EPLDs sit in the broader hierarchy of programmable logic: simple PLD -> EPLD/CPLD -> FPGA. The EP910 family uses a unified architecture with a global programmable interconnect bus that ties 24 macrocells to 12 dedicated inputs and 24 bidirectional I/O pins, supporting up to 36 logic inputs and delivering 240 product terms for sum-of-products logic implementation. Erasable windowed packages allow design iteration via UV erasure, which was the standard development flow for this device family. Key features include 24 macrocells, 12 dedicated inputs, 24 I/O pins, 36 usable inputs, 240 product terms, a 40 ns tPD (pin-to-pin delay), and a low-power CMOS technology node. The PLCC-44 J-lead surface-mount package enables socketed programming and easy rework, an important feature for legacy designs still in production or maintenance. The device is non-volatile (UV-erasable) and supports JEDEC-standard programming algorithms via industry-standard PLD programmers. Typical applications include industrial control glue logic, address decoding and bus interface logic for legacy microprocessors (8086, 68000, Z80), state-machine controllers, peripheral chip replacement, and glue-logic consolidation in mixed-vintage PCB assemblies. The low-power CMOS 'L' variant is well suited to battery-backed or thermally-constrained enclosures where standard NMOS/CMOS EPLDs would exceed thermal budgets. When designing with this device, confirm programmer algorithm support because not all modern universal programmers retain the legacy Classic-series JEDEC file flow. For new designs, consider the modern equivalent EP910LC-40 or evaluate whether a low-density MAX II CPLD or CoolRunner-II family member offers equivalent logic density with lower power, in-system programmability, and a longer active lifecycle.
EP910LI-40T - 24 Macrocells Classic EPLD, 40ns | Altera / Intel
The Altera EP910LI-40T is a member of the Altera Classic EPLD (Erasable Programmable Logic Device) family, manufactured on advanced CMOS technology with a PAL-type architecture. It integrates 24 macrocells interconnected by a global programmable interconnect array, 12 dedicated inputs, and 24 bidirectional I/O lines, supporting up to 36 inputs and 24 outputs with 240 product terms distributed across the logic array. The "-40" speed grade denotes a 40 ns pin-to-pin propagation delay (tPD), and the "T" suffix denotes tape-and-reel packaging. The "L" grade indicates low-power CMOS operation, while "I" denotes the industrial operating temperature range of -40C to +85C. An EPLD (Erasable Programmable Logic Device) is a type of programmable logic that uses EPROM or EEPROM cells to store configuration, allowing the device to be erased with ultraviolet light and reprogrammed many times. EPLDs sit in the programmable logic hierarchy below modern CPLDs (Complex PLDs) and FPGAs, but they offer deterministic timing, low quiescent power, and simple development flows well suited to glue logic, state-machine replacement, and bus-interface decoding in legacy industrial systems. The EP910 family represents Altera's mid-density Classic tier above the EP610 and below the EP1800, providing balanced logic density for medium-complexity designs. Key features of the EP910LI-40T include 24 macrocells, 24 I/O pins, 12 dedicated inputs, 240 product terms, 40 ns tPD propagation delay, CMOS low-power technology, UV-erasable windowed ceramic or plastic package options, and JTAG-free programming via the Altera programming algorithm. The device operates from a single 5 V supply typical of TTL-era logic and is housed in a 40-pin ceramic DIP (J44) or PLCC (J68) package depending on suffix. Industrial temperature range (-40C to +85C) makes it suitable for factory automation and outdoor equipment. Typical applications include bus-interface decoding (address decoding for 8086, 68k, MIPS systems), state-machine replacement, custom peripheral controllers, vintage computer motherboard glue logic, and industrial control legacy equipment. Its deterministic 40 ns delay and 5 V CMOS compatibility make it ideal for replacing discrete 74LS/74HC logic arrays with a single integrated solution, simplifying PCB layout and reducing board area. When designing with the EP910LI-40T, engineers must use Altera's legacy MAX+PLUS II or AHDL development environment (modern Intel Quartus does not support Classic EPLDs), which requires Windows XP or DOS-era emulation. Programming requires a Master Programming Unit (MPU) or compatible third-party programmer, as the device predates JTAG and modern ISP interfaces. Designers should verify availability through authorized distributors as the Classic EPLD family has been NRND for over a decade.
EP910LI-50 - 50ns Classic EPLD, 24 Macrocells | Intel / Altera
The Intel / Altera EP910LI-50 is a 50ns propagation-delay member of the Altera Classic EPLD family, integrating 24 macrocells (450 usable gates) in a 40-pin ceramic DIP (LCC equivalent) through-hole package. It is fabricated on advanced CMOS technology and offers a solution to high-speed, low-power logic integration for glue-logic, state-machine, and bus-interface applications that predate modern CPLDs. An EPLD (Erasable Programmable Logic Device) is a non-volatile, UV-erasable logic IC that preceded modern CPLDs and FPGAs, providing deterministic pin-to-pin timing, predictable logic capacity (measured in macrocells), and one-time/erasable programmability. EPLDs sit in the programmable logic hierarchy: PAL -> GAL -> EPLD -> CPLD -> FPGA. Compared with later CPLDs, EPLDs use EPROM/EEPROM cells and typically target lower gate counts, but offer the lowest cost-per-macrocell for simple glue-logic replacement. The Classic family was Altera's first commercially successful CPLD/EPLD line, introduced in the mid-1980s and now sold primarily through authorized distributors and franchised aftermarket channels for legacy industrial and military programs. Key features of the EP910LI-50 include 24 macrocells, 38 available I/O pins (configurable per the Classic architecture), 50ns tPD (pin-to-pin delay), and 5V CMOS-compatible I/O. The 'I' suffix indicates an industrial temperature grade of -40C to +85C, and 'L' denotes the ceramic DIP package (CERDIP), commonly specified for military and aerospace legacy sustainment programs. Per the Verified Web Data, this MPN is sourced today primarily through Rochester Electronics (an authorized Altera/Intel legacy distributor) and through major FPGA specialist distributors. The device's architecture combines programmable AND/OR arrays with registered macrocell outputs, supporting both combinatorial and synchronous logic at predictable 50ns worst-case delays. Programmability is via standard EPROM programmers; the windowed CERDIP package allows UV erasure for prototype reuse. Per the Alldatasheet index, the EP910 family datasheet is 41 pages and describes the full Classic architecture including macrocell configuration, JTAG-style programming, and AC/DC specifications. Typical applications include legacy 5V industrial controllers, MIL-STD-1553 / ARINC-429 bus glue-logic, vintage computer peripheral adapters, military/aerospace sustainment programs, and prototyping replacements for discrete 74LS logic arrays. Because the EP910LI-50 is a Classic family part, it is widely used in long-lifecycle defense and aerospace systems where design re-qualification is cost-prohibitive. Designers should note that the EP910LI-50 requires a 5V +/- 10% supply, draws up to ~150 mA quiescent, and has no in-system programmability - programming requires a UV-erasable window or a one-time-programmable (OTP) variant. For new designs, modern MAX II or MAX V CPLDs in equivalent logic capacity offer in-system programmability and lower power, but are not pin-compatible. Refer to the manufacturer datasheet for full timing, programming, and reliability specifications.
EP910LI44 - Classic EPLD, 24 Macrocells, PLCC-44 | Altera / Intel
The Altera EP910LI44 is a member of the Classic EPLD family of CMOS Erasable Programmable Logic Devices, featuring 24 macrocells in a 44-terminal PLCC (J-lead) package. It supports up to 12 dedicated inputs and 24 bidirectional I/O pins, for a combined maximum of 36 inputs and 24 outputs. The device is fabricated on advanced CMOS technology and is part of the original Altera Classic EPLD series, now owned and supported by Intel following the 2015 acquisition of Altera. A programmable logic device (PLD) is a general-purpose digital IC whose logic function and interconnects are defined by the user after manufacture. The Altera Classic family belongs to the broader category of programmable logic devices (PLDs), which sit hierarchically between discrete logic gates (74-series TTL) and higher-density FPGAs. Within that taxonomy, the EP910 is a CMOS One-Time-Programmable (OT PLD) PAL-type architecture positioned for glue-logic integration in 5V systems where deterministic pin-to-pin propagation delay and low cost outweigh the need for SRAM-based re-programmability. Key features of the EP910LI44 include 24 macrocells, a maximum propagation delay in the range of 35 to 50 ns depending on speed grade (the suffix -30 / -35 / -40 indicates tpd), up to 24 flip-flops for registered logic, and support for 2 global clock pins. The device operates from a single 4.75 V to 5.25 V supply (industrial version 4.5 V to 5.5 V) and is available in commercial (0 °C to +70 °C) and industrial (-40 °C to +85 °C) temperature grades, as denoted by the L in the part number. Architecturally, the EP910 implements a sum-of-products AND/OR array feeding 24 output macrocells, each of which can be configured as combinational, registered, or I/O. The PAL-type structure gives every macrocell a fixed, predictable fan-in, allowing designers to compute worst-case propagation delay before synthesis - an important advantage over early FPGAs. Programmable interconnect distributes signals across the device with uniform delay, simplifying timing closure for state machines, address decoders, and bus-interface glue logic. Typical applications include 24 mA bus-interface drivers, state-machine controllers, address decoding in 5 V microprocessor systems, and replacement of multiple 74-series TTL packages. Because the EP910 is erasable (UV window on ceramic variants) or one-time programmable (plastic OTP), it suits both prototyping and low-to-medium volume production. Industrial users find the LI temperature grade suitable for factory-floor equipment, telecom peripherals, and consumer-electronics mainboards. When designing with the EP910LI44, plan power-rail decoupling with a 0.1 µF ceramic capacitor close to each supply pin and a bulk 10 µF electrolytic near the package. The EP910 has no internal pull-ups on I/O pins, so external 10 kΩ pull-ups are recommended on unused inputs to prevent floating CMOS inputs. Designers must also respect the 5 V VCC range; connecting to 3.3 V logic requires a level-translator, which the EP910 does not include. This page synthesizes distributor pricing, JTAG/ISP programming alternatives, and practical design notes for the EP910 Classic EPLD family that are not consolidated in the original manufacturer datasheet.
EP910LI44-35 - 24-Macrocell Classic EPLD, 35ns, PLCC-44 | Intel / Altera
The Intel / Altera EP910LI44-35 is a 24-macrocell Classic-series Erasable Programmable Logic Device (EPLD) fabricated on advanced CMOS technology and housed in a 44-pin PLCC package. It delivers a maximum clock frequency of 37 MHz with a propagation delay of 35 ns (tPD), supporting up to 2 external clocks and offering a PAL-type macrocell architecture for high-speed, low-power logic integration. An EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic device that combines the integration density of a PLD with the erasability of UV-erasable EPROM technology. Classic EPLDs sit within the broader programmable logic hierarchy: PAL < EPLD < CPLD < FPGA. They are typically deployed as glue logic, state-machine controllers, and bus-interface bridges where deterministic timing, low standby power, and instant-on (zero-configuration) behavior are required - qualities that modern SRAM-based FPGAs cannot match without an external boot PROM. Key features of the EP910LI44-35 include 24 macrocells organized in a PAL-type logic array, 10 dedicated input pins, 24 I/O pins, a tPD of 35 ns, a maximum internal counter frequency of 37 MHz, and CMOS-level I/O. The device supports in-system programmability via the Altera programming algorithm and is offered in both commercial and industrial temperature grades. The PLCC-44 (J-lead) package provides reliable through-hole soldering for legacy and industrial designs. Architecturally, the EP910 uses Altera's Classic macrocell with a product-term array feeding an OR gate, a programmable register, and a tri-state output buffer. Each macrocell supports D, T, JK, or SR flip-flop modes. The I/O architecture supports true bidirectional and registered I/O, and the device includes global clock networks routed through dedicated pins for low-skew distribution. Power consumption is typically below 200 mW at full operation, with CMOS standby currents in the microamp range when the device is not switching. Typical applications for the EP910LI44-35 include legacy industrial control, military/aerospace systems with long lifecycle requirements, telecom infrastructure glue logic, address decoding and bus arbitration in 8086/68k-based designs, and replacement of discrete 74LS/74HC logic in cost-sensitive applications. The 35 ns speed grade is well-matched to microcontrollers and microprocessors of the 1980s-1990s generation. When designing with this EPLD, ensure that the design fits within 24 macrocells and uses only the supported product-term count per macrocell. Use the MAX+PLUS II or Quartus legacy support tools to compile the design, and program the device using an Altera-compatible programmer. The PLCC-44 socket is recommended for prototyping. This page synthesizes distributor pricing, drop-in same-package alternatives, and practical design notes not found in the manufacturer datasheet, helping engineers sustain long-lifecycle EPLD-based systems.
EP910PC-0 - Classic EPLD, 24 Macrocells, 40-Pin PDIP | Altera
The Altera EP910PC-0 is a Classic-series Erasable Programmable Logic Device (EPLD) that delivers 24 macrocells and approximately 900 usable gates in a 40-pin Plastic DIP (PDIP-40) package. It is fabricated on advanced CMOS technology, offers 100% TTL emulation, and integrates multiple PAL/GAL-type devices into a single low-power, high-speed solution. The "PC" suffix denotes the PDIP-40 plastic commercial package, while "-0" indicates the slowest speed grade in the Classic EPLD family. An EPLD (Erasable Programmable Logic Device) is a type of programmable logic IC that combines multiple PAL/GAL-style AND/OR arrays with a shared programmable interconnect and a fixed OR array of macrocells. EPLDs sit in the taxonomy below modern CPLDs and FPGAs: programmable logic -> CPLD/EPLD -> PAL/GAL replacement -> logic integration IC. The Classic EPLD family was Altera's flagship low-density glue-logic replacement family in the late 1980s and 1990s, offering 100% TTL-compatible I/O and in-system erasability via a quartz window or, for plastic packages, one-time-programmable (OTP) UV-erasable silicon. Key features of the EP910PC-0 include 24 macrocells, 10 dedicated input pins, 24 I/O pins, a maximum propagation delay in the slowest ("-0") speed grade, 5V single-supply operation, and TTL-compatible logic thresholds. The device is implemented in CMOS technology for low power consumption, with each macrocell containing a programmable AND/OR array and a flip-flop. The Classic EPLD macrocell architecture enables pin-to-pin replacement of multiple 20- and 24-pin PAL/GAL devices, dramatically reducing board area and part count in legacy logic designs. Typical applications include TTL glue-logic replacement, bus-interface decoding, state-machine implementation, address decoding for microprocessor systems, and consolidation of multiple PAL/GAL devices in industrial control, telecommunications, and military/aerospace systems. The PDIP-40 through-hole package is favored for prototype development, breadboarding, and legacy systems where socketed parts simplify field serviceability. When designing with the EP910PC-0, engineers should note that the "-0" speed grade is the slowest available; for time-critical paths, the "-15", "-20", "-25", "-30", or "-35" grades provide progressively faster propagation delays in the same PDIP-40 footprint. This page synthesizes distributor pricing, drop-in same-package alternatives, and practical design notes for engineers maintaining or replicating legacy Altera Classic EPLD designs.
EP910PC-15 - 900-Gate Classic EPLD, 15ns PDIP | Altera
The Altera (now Intel) EP910PC-15 is a 900-usable-gate member of the Altera Classic EPLD family, a high-performance CMOS erasable programmable logic device offering pin-to-pin logic delays as low as 10 ns and counter frequencies as high as 100 MHz. The "-15" speed grade denotes the 15 ns tpd tier, and the "PC" suffix indicates a plastic dual in-line package (PDIP). The Altera Classic family targets high-speed, low-power logic integration, allowing designers to consolidate multiple PAL- and GAL-type devices into a single non-volatile part with densities spanning 300 to 900 usable gates. An EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic device that combines the architectural simplicity of a PLA (programmable AND / fixed OR) with on-chip macrocells and a one-time- or UV-erasable CMOS process. In the system hierarchy, EPLDs sit between simple SPLDs/PALs and modern FPGAs, historically serving as glue-logic replacements that retain their configuration without a boot PROM. The Classic family is fabricated on advanced CMOS technology and supports 100% TTL emulation, making the EP910 a direct substitute for clusters of 20-pin and 24-pin PAL/GAL devices. Key features of the EP910PC-15 include 24 macrocells, 10 dedicated input pins, 12 dedicated I/O pins, and a maximum toggle frequency of 100 MHz. The device operates from a single 5 V supply (VCC range 4.75 V to 5.25 V), draws Icc of typically 80 mA, and is packaged in a 24-pin, 0.300-inch-wide PDIP with through-hole leads. Programming is performed via the Altera Logic Programmer card on a standard PC parallel port. Architecturally, the EP910 implements a sum-of-products PLA with a global interconnect and per-macrocell flip-flops with configurable D/T/JK/SR modes. Programmable output slew-rate control reduces ground bounce on heavily-loaded buses, and unused pins can be left open without damage - though the datasheet recommends enabling the internal pull-up resistor via the configuration bit. Typical applications include TTL-logic replacement, address decoding for microprocessor systems, state-machine controllers, and bus-interface glue logic. Industrial control boards from the 1990s frequently use the EP910 as a peripheral decoder or interrupt controller. Because the part is in sustained production for legacy and long-lifecycle programs, it remains a popular choice for military, aerospace, and industrial sustainment designs. When designing with the EP910PC-15, observe the 0.3-inch PDIP-24 footprint and provide a 0.1 uF decoupling capacitor adjacent to VCC. The device is obsolete on Altera's modern price book; long-term procurement should target franchised distributors holding date-code inventory rather than the open market.
EP910PC-15T - 24-Macrocell EPLD, 15ns, PDIP-40 | Altera Classic
The Altera EP910PC-15T is a member of the Altera Classic EPLD family, an erasable programmable logic device (EPLD) with 24 macrocells and 10 dedicated input pins, fabricated on advanced CMOS technology and housed in a 40-pin plastic DIP (PDIP-40) package. Key headline specifications include a 15 ns pin-to-pin logic delay (tPD), a 24-macrocell AND-array architecture, and 10 dedicated input pins that fan into a programmable AND array feeding the 24 macrocell output registers. The '-15T' suffix denotes the 15 ns speed grade with Tape and Reel packaging. An EPLD (Erasable Programmable Logic Device) is a member of the programmable logic hierarchy, sitting between simple PLDs (PAL/GAL) and modern FPGAs/CPLDs. EPLDs use a sum-of-products architecture with a programmable AND array feeding fixed OR gates and output macrocells, packaged in UV-erasable or one-time-programmable CMOS silicon. The Classic family was Altera's second-generation EPLD line, replacing discrete TTL/CMOS gate arrays with single-chip, user-programmable logic for glue functions, state machines, and bus-interface logic. Key features include 24 macrocells each containing a programmable flip-flop with separate feedback, output enable, and programmable output polarity, plus 10 dedicated input pins (no input/output pin multiplexing) that simplify pin-locked designs. Device programming uses the Altera LogicMap or MAX+PLUS II design flow with industry-standard JEDEC fuse-map files. The EP910 also supports security-bit protection to lock the design after programming. Architecturally, the EP910 implements a global bus-driven AND plane with 72 product terms feeding 24 macrocells, yielding 24 registered outputs that can be configured as combinational (bypass register) or registered. The device is non-volatile (UV-erasable on ceramic-windowed versions, OTP on plastic packages), operates from a single 5 V supply, and delivers TTL-compatible I/O with 24 mA sink current per output. Typical applications include bus-interface glue logic, address decoding for microprocessor systems, peripheral control state machines, and replacement of multiple discrete 74LS/74F TTL parts. Modern designs typically substitute the EP910 with a CoolRunner-II CPLD or MAX II CPLD, but the Classic EP910 remains in service for legacy industrial, military, and avionics systems where pin-compatible replacements are required. Design considerations: the 15 ns speed grade is the slowest in the EP910 family (the family spans 10-25 ns); the suffix '-15T' includes tape-and-reel packaging. Plan for end-of-life risk - Altera discontinued the Classic EPLD family years ago, so sourcing is limited to authorized distributors and the broker/excess market. This page synthesizes datasheet parameters, drop-in Altera Classic family variants, parametric comparison data, and practical design notes not found in a single manufacturer document.
EP910PC-20 - Classic EPLD, 900 Gates, 20ns DIP-24 | Altera
The Altera EP910PC-20 is a 900-usable-gate Classic EPLD from the Altera Classic device family, supplied in a 24-pin PDIP (PC) package with a 20 ns pin-to-pin propagation delay. The Classic family delivers high-speed, low-power CMOS logic integration for glue-logic and bus-interface applications where multiple PAL or GAL devices would otherwise be required. A Classic EPLD (Erasable Programmable Logic Device) is a one-time-programmable (windowed EPROM-based) or UV-erasable CMOS PLD that replaces discrete SSI/MSI logic and small PAL/GAL arrays. EPLDs sit in the programmable logic hierarchy below CPLDs and FPGAs, offering non-volatile, deterministic logic with predictable timing. The Classic family specifically targets pin-to-pin speeds competitive with TTL and 74-series logic while consuming CMOS standby power. Key features of the EP910PC-20 include 24 pins, 16 dedicated inputs and 8 dedicated outputs (configurable as I/O depending on family mode), 900 usable gates, 100% TTL compatibility, and a 20 ns worst-case tPD (suffix "-20" speed grade). The part is fabricated on advanced CMOS technology and provides pin-to-pin logic delays suitable for state-machine decoding, address decoding, and bus-interface glue logic. The EP910 family integrates 300 to 900 usable gates, replacing multiple PAL/GAL devices with a single package. The EP910 architecture combines a sum-of-products AND/OR array with output macrocells featuring programmable polarity, registered or combinatorial outputs, and feedback paths. Programming is performed via a standard EPROM programmer using the JEDEC fuse-map format, and the device is non-volatile at power-up. The Classic family includes 100% TTL I/O compatibility and supports both 5V-only and mixed-voltage system designs. Typical applications include address decoding for microprocessor systems, bus arbitration, state-machine controllers, peripheral interface glue logic, and replacement of multiple PAL/GAL devices with a single EPLD. The PDIP-24 footprint supports through-hole PCB assembly, breadboard prototyping, and legacy system maintenance where socketed logic must remain in place. Designers should select the -20 speed grade when a 20 ns maximum tPD is sufficient for the target system clock or address-to-enable timing. Slower grades (-25, -30, -35) offer lower cost where timing margins permit. Faster -15 and -12 grades exist for tighter timing budgets. This page synthesizes distributor pricing, drop-in same-family alternatives, and practical design notes not found in the manufacturer datasheet alone.
EP910PC-20T Classic EPLD | Altera | Logic Integration
Altera EP910PC-20T is a member of the Classic EPLD family, a CMOS programmable logic device intended for high-speed, low-power logic integration. The verified search data identifies the family as supporting high-speed, low-power integration and as using advanced CMOS technology. It is described as a solution for integrating multiple PAL- and GAL-type devices, with Classic EPLD densities ranging from 300 to 900 usable gates. The EP910PC-20T ordering information specifically denotes the PC package and 20 ns speed grade, but the exact package pin count, electrical limits, memory architecture, and I/O count are not present in the supplied web excerpts. [DATA_NEEDED: package pin count and package dimensions]. An EPLD is an erasable programmable logic device: an integrated circuit whose logic functions are configured by the user and can be erased and reprogrammed. EPLDs sit within the programmable logic hierarchy between simple PLDs and larger FPGA devices. They combine programmable AND/OR logic, fixed interconnect, and input/output blocks in a nonvolatile architecture, making them useful for replacing multiple discrete PAL and GAL devices. The Classic EPLD family provides a compact way to implement glue logic, registered state machines, decoders, counters, and interface conditioning in a single programmable component. The EP910PC-20T is presented as a high-speed, low-power Classic EPLD. Its family-level positioning targets logic integration rather than the large sequential or signal-processing workloads commonly addressed by FPGAs. The supplied material states that the family supports 100% TTL emulation and that the EP910PC provides pin-to-pin logic integration for multiple PAL- and GAL-type devices. The 20 ns ordering suffix is treated as the device's specified speed grade, but a precise maximum operating frequency, propagation delay measurement condition, and power-consumption value are not available in the verified excerpts. The CMOS fabrication process supports the family's low-power objective while providing the speed needed for conventional TTL-compatible digital logic. Unlike a fixed-function logic IC, the EP910PC-20T can be programmed for a particular board's decoding, control, or interface requirements. Unlike an FPGA, its smaller Classic EPLD architecture is generally associated with simpler logic integration and a more focused capacity range, although the supplied data does not state a direct comparison of internal resources. Potential applications include legacy TTL logic consolidation, programmable address decoding, state-machine control, industrial control interfaces, and replacement of several PAL- or GAL-type devices on a board. The part is especially relevant to maintenance and redesign work involving existing Altera Classic EPLD designs, where changing the footprint or programming architecture may require board or firmware changes. Before new production use, verify the exact package drawing, supported programmer, software toolchain, and lifecycle status. For design-in, confirm that the selected package, pinout, operating voltage, temperature range, timing grade, and programming procedure match the existing implementation. Do not infer electrical limits from the family description. Use the manufacturer datasheet and an approved programming workflow before relying on the part for a new design. This page combines the verified EP910PC-20T search evidence, family-level application context, explicit missing-data markers, and replacement-screening guidance. It is intended to help engineers distinguish confirmed facts from parameters that require a full datasheet or device-specific cross-reference check.
EP910PC-25 - 900-Gate Classic EPLD, 25ns, PDIP-24 | Intel / Altera
The Intel / Altera EP910PC-25 is a 900-usable-gate member of the Classic EPLD (Erasable Programmable Logic Device) family, supplied in a 24-pin plastic DIP (PDIP-24) package with a 25 ns pin-to-pin logic delay. It is fabricated on advanced CMOS EPROM technology and is intended for high-speed, low-power logic integration, replacing multiple PAL/GAL devices with 100% TTL emulation. What is an EPLD? An EPLD is an Erasable Programmable Logic Device - a non-volatile programmable logic IC that sits in the hierarchy between simple PLDs (PAL/GAL) and modern FPGAs. It uses EPROM/EEPROM cells to store the AND/OR array fuse pattern, can be erased with UV light, and offers deterministic pin-to-pin timing ideal for glue-logic, bus decoding, and state-machine applications. The Classic family occupies the legacy PAL-replacement niche and is widely used in industrial control, instrumentation, and legacy system designs. Key features include 24 macrocells, 10 dedicated inputs, 12 dedicated input/output pins (bidirectional), 900 usable gates, 4800 integration gates (typical), and 100% TTL-compatible I/O. The EP910PC-25 provides 25 ns tPD (pin-to-pin delay) and operates at fMAX around 33.3 MHz with a 5 V +/- 10% supply. The CMOS EPROM process ensures low standby power, and the ceramic/erasable variants are suitable for prototype development while the plastic PDIP-25 suffix targets production. Architecturally the EP910 uses a sum-of-products (AND-OR) array feeding a fixed set of macrocells with programmable output polarity, feedback, and output enable. Output logic macrocells (OLMCs) can be configured as registered or combinatorial, allowing sequential and combinatorial logic in the same device. The deterministic timing model allows classic synthesis tools and Abel/CUPL/PLDshell design flows. Typical applications include TTL glue-logic replacement, address decoding for microprocessor/microcontroller buses, peripheral interface adapters (PIA), state machines in industrial controllers, and legacy 5V system integration. The PDIP-24 form factor supports through-hole assembly for repair-friendly and industrial designs. Design consideration: The "PC" suffix indicates PDIP-24 plastic commercial-grade, while the "-25" indicates 25 ns tPD. The part is windowless (one-time-programmable from the user's perspective) since the plastic package blocks UV erasure - plan accordingly for prototyping with a ceramic-windowed variant (DIP/LI). This page consolidates distributor pricing for the EP910PC-25, cross-brand EPLD drop-in alternatives sharing the PDIP-24 footprint, and practical design notes covering programming, supply decoupling, and pinout that complement the manufacturer datasheet.
EP910PC-30 - 24-Macrocell Classic EPLD, 30ns, PDIP-40 | Altera
The Altera EP910PC-30 is a Classic-family Erasable Programmable Logic Device (EPLD) delivering 24 macrocells and approximately 450 usable gates in a 40-pin Plastic DIP (PDIP-40) package. The "PC" suffix denotes the plastic through-hole package, while "-30" designates a 30 ns worst-case pin-to-pin propagation delay, corresponding to a maximum counter frequency of 33.3 MHz. The device operates from a single 5 V supply and supports 100% TTL emulation for direct drop-in replacement of discrete PAL and GAL logic arrays. What is an EPLD? An EPLD (Erasable Programmable Logic Device) is a member of the programmable logic family that sits architecturally between simple PAL/GAL SPLDs and higher-density CPLDs. An EPLD combines multiple macrocell-based logic blocks into a single package, allowing designers to consolidate dozens of 7400-series TTL functions into one UV-erasable IC. EPLDs occupy the middle rung of the hierarchy: SPLD (PAL/GAL) -> EPLD (Classic, MAX) -> CPLD (MAX II/3000, MAX V) -> FPGA. The EP910 is part of Altera's Classic family, the second generation of the MAX architecture. Key features include 24 macrocells organized into four Logic Array Blocks (LABs) with 36 dedicated input pins and 12 bidirectional I/O pins, programmable output macrocells with flip-flops (D, T, JK, SR), asynchronous clear and preset, programmable I/O architecture supporting combinatorial or registered outputs, and on-board logic test circuitry to verify AC parameters during production. The EP910 implements sum-of-products logic via a programmable AND/OR array with feedback paths that enable complex state machine implementation. Typical applications include glue-logic consolidation for 8086/68000-era microprocessor systems, address decoding and bus interfacing, state-machine controllers, peripheral replacement of multiple PAL/GAL devices, and legacy industrial control retrofits. Designers targeting modern designs typically migrate to MAX II or MAX V CPLDs, but the EP910 remains in service for repair of installed equipment and exact-form-factor replacements. When designing with the EP910, ensure logic equations fit within the available 24-macrocell / 36-input product-term budget; synthesis tools such as MAX+PLUS II perform fitting and report resource utilization. Programming requires a compatible EPROM/UV eraser or Altera programming hardware, since Classic EPLDs are erasable rather than in-system programmable. The 5 V supply tolerance (±10%) is critical for TTL compatibility, and decoupling capacitors should be placed within 0.5 inches of each VCC/GND pair. This page synthesizes distributor pricing, current lifecycle status from Rochester Electronics, drop-in same-package alternatives within the EP910 family, and practical design notes not consolidated in the original Altera datasheet.
EP910PC-30T - 900-Gate Classic EPLD, 30ns, DIP-40 | Intel (Altera)
The Intel (formerly Altera) EP910PC-30T is a 900-usable-gate Classic EPLD with 30 ns pin-to-pin propagation delay, 24 macrocells, 24 I/O pins, and 12 dedicated inputs, fabricated on an advanced CMOS process and packaged in a 40-pin plastic DIP (PDIP-40). It is designed for high-speed, low-power logic integration in through-hole legacy designs and supports a maximum clock frequency of 33.3 MHz, 100% TTL emulation, and pin-to-pin compatibility with other EP910 speed grades. An EPLD (Erasable Programmable Logic Device) is a type of programmable logic that replaces multiple discrete PAL/GAL devices with a single CMOS IC; in the broader taxonomy it sits between simple PLDs (PAL/GAL) and modern CPLDs/FPGAs as an early high-density, UV-erasable logic family. The Classic family provides densities from 300 to 900 usable gates and propagation delays as low as 10 ns, making it a workhorse for industrial control, glue logic, and bus-interface bridging where modern FPGAs would be over-spec and over-priced. Key features include 240 product terms across 24 macrocells interconnected by a global programmable interconnect array, 100% TTL-compatible I/O, on-board logic test circuitry for AC verification during production flow, and programming compatibility with the MAX+PLUS II development system. The 'PC' package suffix denotes plastic DIP, while '-30T' indicates the 30 ns speed grade in tube packaging, identical to the commercial EP910PC-30 except for delivery format. Architecturally the EP910PC-30T uses a PAL-type AND/OR structure with a global bus connecting each macrocell, supported by a 5 V CMOS process that delivers low quiescent power compared to bipolar TTL PLDs. Each macrocell contains an XOR gate, a programmable flip-flop, an output enable, and a feedback path, allowing registered, combinational, and bidirectional I/O configurations within the same device. The Classic family's logic test circuitry allows verification of function and AC specifications during standard production flow. Typical applications include industrial control glue logic, address decoding and bus interfacing for legacy microprocessors (e.g., 8086, 68000, Z80 systems), state-machine replacement of discrete SSI/MSI logic, custom peripheral controllers in test equipment, and pin-compatible upgrades of older EP310/EP320 designs. It is commonly used to consolidate multiple 16L8/20L8 PALs into a single device, simplifying PCB layout and reducing part count. When designing with this device, ensure your design tools support the Classic device family (MAX+PLUS II or compatible legacy software). Verify the 30 ns propagation delay meets your timing budget against the slowest clock edge in your system. Plan for end-of-life sourcing: the Classic family is mature and inventory is mostly distributor or aftermarket stock; second-source or upgrade paths should be evaluated for new long-life designs. This page synthesizes distributor pricing, same-package drop-in alternatives within the EP910 family, and practical design notes not found in the original Altera datasheet, giving engineers a single reference for sourcing and implementing the EP910PC-30T.
EP910PC-35 - 35ns 24-Macrocell EPLD | Altera | Classic EPLD
The Altera EP910PC-35 is a 24-macrocell high-performance CMOS Erasable Programmable Logic Device (EPLD) from the Classic EPLD family, specified at 35 ns pin-to-pin propagation delay. Housed in a 40-pin Plastic DIP (PDIP) package, the EP910PC-35 delivers up to 37 MHz counter frequency and 100 MHz internal performance, making it a staple glue-logic building block for legacy industrial, telecom, and test equipment designs. An EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic device from the pre-FPGA era, providing PAL-type sum-of-products logic with on-chip macrocells, a programmable AND/OR array, and reconfigurable I/O architecture. EPLDs sit in the programmable logic hierarchy between simple PAL/GAL devices and modern FPGAs, and the EP910 family specifically targets designs that need higher density and I/O count than 22V10-class devices while avoiding the complexity of SRAM-based FPGAs. The EP910PC-35 is the UV-erasable/OTP plastic-DIP variant of the EP910 family. Key features include 24 macrocells with 24 I/O pins, 12 dedicated inputs giving 36 total inputs, 240 product terms distributed across the AND-array, and 35 ns typical pin-to-pin logic delay. The PAL-type architecture with buried macrocell registers, combined with CMOS technology, provides low power consumption and high noise immunity. The device operates from a single 5V supply and is in-system programmable via Altera's classic A+PLUS or MAX+PLUS development tools. Architecturally, the EP910 family combines a global interconnect scheme with per-macrocell product-term allocation, allowing wide combinational and registered logic functions without the routing congestion of older PALs. Macrocell flip-flops can be configured as D, T, JK, or SR, with selectable clock polarity and asynchronous clear/preset — giving designers flexibility comparable to early 1990s PLDs. Typical applications include address decoding and bus interface logic in 5V embedded systems, replacement of multiple 22V10 / 16L8 PALs in industrial controllers, glue logic in legacy telecom backplanes, and prototyping or low-volume production where FPGAs are over-specified. The plastic DIP package simplifies hand-soldering and rework on through-hole boards. When designing with this device, ensure your programming tool supports the EP910 family — A+PLUS or MAX+PLUS legacy software is required. Note that plastic DIP packages are not windowed for UV erasure; use ceramic windowed CerDIP variants (EP910DC-35) during development and plastic for production. Decoupling: place a 0.1 uF capacitor on each VCC pin and minimize high-current switching near the device. This page synthesizes distributor pricing, drop-in same-family EPLD alternatives (EP910PC-30, EP910PC-25), cross-reference compatibility information, and practical design notes that complement the manufacturer datasheet for legacy designs.
EP910PC/PI - 900-Gate CMOS Classic EPLD | Intel | PDIP-40
The Intel (formerly Altera) EP910PC/PI is a 900-gate member of the Altera Classic EPLD family, fabricated on advanced CMOS technology and offering high-speed, low-power logic integration in a 40-pin PDIP through-hole package. It provides 24 macrocells, 48 flip-flops, 33.3 MHz fMAX, and 5 V operation with 100% TTL emulation and 10 mA/24 mA I/O drive strength. The 'PC' suffix denotes a 0 to 70 °C commercial-temperature PDIP package, while the dual 'PC/PI' marking covers both the commercial- and industrial-temperature options for the same footprint. A Classic EPLD (Erasable Programmable Logic Device) is a non-volatile, UV-erasable CMOS PLD that combines PAL/GAL-like AND/OR arrays with on-chip macrocell flip-flops, forming an early predecessor of today's flash-based CPLDs. Within the broader programmable-logic hierarchy, Classic EPLDs sit below MAX II/MAX V CPLDs and modern Cyclone/MAX FPGAs in density but above discrete 22V10 PALs in functional capability. They are typically programmed with the MAX+PLUS II development toolchain via a JTAG/ISP or device-programmer interface. Key features of the EP910PC/PI include 100% TTL-compatible I/O, JTAG-based boundary-scan testability, 24 dedicated input pins, 48 I/O pins, and 33.3 MHz system-clock performance. The CMOS EPROM-style configuration cell yields zero standby power on legacy unconfigured cells, and the on-board logic test circuitry allows AC specification verification during production flow. These attributes made the EP910 a popular glue-logic replacement for multiple PAL and GAL devices in 5 V industrial and telecom designs of the 1990s. Architecturally, the EP910 integrates a global programming array, a macrocell array with 24 flip-flops, an I/O control block, and dedicated input pins. The Classic architecture pioneered macrocell sharing, which became a defining feature of subsequent MAX-series CPLDs. Designers using the EP910PC/PI can implement 100% pin-to-pin logic integration while maintaining deterministic 25 ns propagation delays for state-machine and bus-interface logic. Typical applications include TTL/CMOS glue-logic replacement, address decoding, state machines, bus arbitration, and 5 V system controllers in industrial automation, telecommunications backplane controllers, and legacy military/aerospace systems (when the /883B-screened DM variants are used). The wide 5 V tolerance makes it well suited to 5 V-only legacy backplanes. When designing with the EP910PC/PI, ensure the device is programmed before PCB-level in-system programming is finalized, since legacy UV-windowed variants require a quartz-windowed CERDIP package for erasure. Decoupling should follow Altera's 0.1 µF per VCC pin guideline with a single 10 µF tantalum bulk capacitor. Pin-compatibility across the EP910 speed grades (-15, -20, -25, -30, -35) simplifies PC-grade PCB reuse.
EP910PC30T - 24 Macrocells CMOS Classic EPLD, 30ns DIP-24 | Altera
The Altera (Intel) EP910PC30T is a 30ns, 5V Classic EPLD with 24 macrocells and 24 I/O pins in a 24-pin PDIP through-hole package. It belongs to the Altera Classic device family, fabricated on advanced CMOS technology for high-speed, low-power logic integration in glue-logic and bus-interface roles. A Classic EPLD (Erasable Programmable Logic Device) is a one-time- or UV-erasable PLD that preceded modern CPLDs and FPGAs in the programmable logic hierarchy. The taxonomy runs: programmable logic device (PLD) -> EPLD -> Classic EPLD -> complex PLD (CPLD), positioning the EP910 as a mid-density, low-power, deterministic-delay glue-logic IC that bridges the gap between simple PAL/GAL devices and modern CPLDs such as the MAX 7000 series. Key specifications include 24 macrocells interconnected by a global programmable interconnect, 12 dedicated inputs, 24 I/O lines, up to 240 product terms, a maximum clock frequency of 33.3 MHz, and a propagation delay (tPD) of 30 ns. The device operates from a single 5V supply (typical VCC range 4.75 V to 5.25 V) and offers non-volatile, factory- or user-programmable AND/OR logic arrays. Architecturally, the EP910PC30T uses a PAL-type sum-of-products macrocell structure with a global bus connecting all 24 macrocells, enabling deterministic 30 ns pin-to-pin delays regardless of routing path. The CMOS EPROM-based cell array provides zero standby power once programmed and supports a JEDEC-standard programming algorithm compatible with standard device programmers. Typical applications include address decoding and bus-interface glue logic in 5V microprocessor systems, peripheral-chip replacement in legacy designs, state-machine and sequencer implementation, and industrial control logic where deterministic timing and 5V tolerance are required. The 30 ns speed grade makes it suitable for systems clocked up to 33 MHz. When designing with the EP910PC30T, note that the part is non-erasable (one-time-programmable, OTP) in most package options; only ceramic-windowed packages permit UV erasure. Designers should also confirm 5V I/O compatibility with modern 3.3V logic, as the EP910 lacks 5V-tolerant inputs that would interface directly with low-voltage rails. This page synthesizes distributor stock, same-package speed-grade alternatives, and practical design notes not found in the original 41-page Altera datasheet.
EP910PI-12T - 24 Macrocell Classic EPLD, 12ns tPD | Altera
The Altera EP910PI-12T is a 24-macrocell Classic-series Erasable Programmable Logic Device (EPLD) housed in a 40-pin plastic DIP (PDIP-40) package, with a 12 ns propagation delay and CMOS technology. It belongs to the Classic EPLD family that delivers high-speed, low-power logic integration for glue-logic and state-machine replacement applications. The 'PI' suffix indicates the PDIP-40 industrial-temperature package, and '-12T' indicates the 12 ns speed grade with a Tape-and-Reel or specific test/packaging suffix. An EPLD (Erasable Programmable Logic Device) is a one-time-or-UV-erasable PLD that preceded modern CPLDs and FPGAs. As a product category it sits between fixed logic gates and modern FPGAs in the programmable logic hierarchy: PLD -> EPLD -> CPLD -> FPGA. EPLDs typically offer macrocell-based combinational and registered logic with deterministic timing, non-volatile (UV-erasable) configuration, and instant-on behavior - making them suitable for legacy designs where simplicity and deterministic timing matter more than gate density. Key features of the EP910PI-12T include 24 macrocells interconnected via a global programmable interconnect array, 24 I/O pins, and 12 dedicated inputs supporting two clock domains. Fabricated in CMOS technology, it offers a typical 15 ns pin-to-pin propagation delay (commercial) with the -12 speed grade being the faster variant in this part family. The device supports both combinatorial and registered logic with feedback, and is in-system programmable via a standard JEDEC programming interface. Typical applications for the EP910PI-12T include address decoding, bus interfacing, state-machine control, and glue logic in legacy industrial, telecom, and embedded systems. Engineers selecting this part typically need exact timing behavior, deterministic logic, and pin compatibility with prior Altera Classic designs. It is fully compatible with industry-standard PLD development tools including the Altera MAX+PLUS II legacy flow. Designers should note that the EP910 series is part of the mature Altera Classic EPLD line, now NRND/EOL for new designs. For new designs, consider MAX II, MAX V, or MAX 10 CPLDs as modern equivalents. The PDIP-40 package simplifies prototyping on through-hole PCBs but limits automated assembly. Pricing reflects legacy/obsolete status and limited supply.
EP910PI-15T - 24-Macrocell Classic EPLD, 15ns | Altera
The Altera EP910PI-15T is a member of the Classic EPLD (Erasable Programmable Logic Device) family from Intel/Altera, providing 24 macrocells, 12 dedicated inputs, and 24 I/O pins interconnected by a programmable AND/OR logic array in a 40-pin plastic DIP package. It is fabricated on advanced CMOS technology and operates from a single 5V supply (4.5V to 5.5V), with a 15ns maximum pin-to-pin propagation delay (tPD) at industrial temperature ranges. A Classic EPLD is an electrically erasable programmable logic device that combines the architectural simplicity of sum-of-products (AND-OR) logic with non-volatile E2PROM memory cells, sitting historically between discrete PAL/GAL devices and modern SRAM-based FPGAs in the programmable logic hierarchy. The EP910 family sits in the classic programmable logic family and is the second largest density member of that series, used for glue-logic integration and state-machine consolidation on 5V systems that predate the 3.3V migration. Architecturally the part is one of the highest-density 5V-only erasable PLDs Altera shipped in the Classic line. Key features include 24 macrocells, a Programmable Interconnect Array (PIA) with deterministic tPD, 24 mA DC output drive per pin (TTL-compatible), pin-compatible JEDEC-standard programming, and 100% factory-tested logic. The device supports both combinatorial and registered logic with feedback, and includes dedicated input pins, output enable control per macrocell, and a global clear/preset. Programming is performed via standard JEDEC fuses using an Altera programming hardware or compatible third-party programmer. The EP910PI-15T is fabricated in a CMOS EEPROM process, draws relatively low standby current for a Classic EPLD, and is supplied in a through-hole 40-pin PDIP package (R-PDIP-T40) suitable for industrial and legacy designs. The PI suffix indicates the plastic DIP package, and the 15 speed grade denotes 15 ns tPD; the trailing T indicates tape and reel packaging for the through-hole part. Typical applications include industrial 5V control logic, glue-logic replacement for discrete 74LS/TTL gates, address decoding and bus interfacing, state-machine implementation, and legacy equipment repair/maintenance. Engineers choose this part when designing or maintaining 5V systems that need non-volatile, deterministic-timing logic without the complexity of an FPGA. When designing with the EP910PI-15T, account for the 15 ns propagation delay in worst-case timing paths and respect the 24 mA per-pin output current limit. Use the Altera MAX+PLUS II or classic development flow for design entry and JEDEC generation. For new designs consider a modern MAX II/V equivalent; for legacy board repair or pin-compatible 5V replacement the EP910PI-15T is a direct-fit option. This page synthesizes Altera datasheet parameters, distributor stock signals, same-package EP910 family variants as drop-in alternatives, and practical 5V glue-logic design notes not assembled in a single place on the manufacturer's datasheet alone.
EP910PI-20 - 24 Macrocell Classic EPLD, 20ns, PDIP-40 | Altera
The Intel / Altera EP910PI-20 is a 24-macrocell Classic EPLD (Erasable Programmable Logic Device) from the original Altera Classic device family, fabricated on advanced CMOS technology, housed in a 40-pin PDIP (Plastic DIP) through-hole package with a 20 ns pin-to-pin propagation delay grade. It targets high-speed, low-power logic integration in glue-logic and bus-interface applications where a small, deterministic PLD offers faster time-to-market than an FPGA. Background Knowledge: An EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic device, sitting in the broader taxonomy of programmable logic: PLD -> EPLD -> CPLD -> programmable logic -> semiconductor. EPLDs were the predecessors to today's CPLDs and offer a small number of macrocells with deterministic timing and zero power-on configuration delay, unlike SRAM-based FPGAs. They were widely used for address decoding, bus arbitration, state-machine control, and peripheral glue logic in 5V-era designs. The EP910 family is the 24-macrocell, 36-pin/40-pin member of the original Altera Classic series, with EP610 (16 macrocells) and EP1810 (48 macrocells) as siblings. Key features of the EP910PI-20 include 24 macrocells organized as 12 dedicated inputs and 24 bidirectional I/O pins (in the PDIP-40 footprint), 20 ns tPD (pin-to-pin delay), a 125 MHz internal counter frequency, and zero standby-power CMOS EPROM technology with UV-erasable windowed packages available for prototyping. The device is 5V-tolerant (VCC = 5V +/- 5%) and offers programmable macrocell flip-flops, product-term allocation, and configurable output polarity. The PI suffix indicates the industrial temperature grade (-40C to +85C). Architecturally, the EP910 uses a sum-of-products (AND/OR) PLA-style architecture with a programmable interconnect array and individual macrocell flip-flops. Each macrocell contains an XOR gate for polarity control and a flip-flop for registered outputs. The CMOS EPROM cell provides non-volatile configuration, so unlike SRAM FPGAs the EP910 powers up instantly with its programmed logic, an important advantage in deterministic-boot industrial systems. Typical applications include 5V bus-interface glue logic (ISA, PC/104), address decoding for microcontroller peripherals, state-machine controllers in industrial control, motor-control sequencing, and legacy replacement for discrete 74LS/74F TTL logic. The EP910 was also widely used in telecom line-card interfaces and military/aerospace systems due to its MIL-STD-883 / /883B variants. Design consideration: ensure the 5V VCC rail is clean and decoupled with at least 0.1 uF ceramic + 10 uF bulk capacitors close to the device. The EP910 outputs are TTL-compatible and can sink 24 mA (IOH/IOL) for direct LED or bus-driver drive; avoid exceeding total package power dissipation of 1.5W. Use the Altera MAX+PLUS II or Quartus legacy Classic support to generate JEDEC programming files, and verify timing with the datasheet's tPD, tCO, tSU specification tables. Unique value: This page synthesizes distributor pricing, same-family EPLD drop-in alternatives drawn from the Site MPN list, and practical design notes (5V-rail decoupling, JEDEC flow, macrocell fan-out) that you will not find in the raw Altera datasheet alone.