10AS032E4F27I3LG vs 10AS032E4F27I3SG Comparaison
Comparaison détaillée côte à côte de 10AS032E4F27I3LG par Intel et 10AS032E4F27I3SG par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | 10AS032E4F27I3LG | 10AS032E4F27I3SG |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $1 085,10 | $1 465,00 |
| Family | Arria 10 SX SoC FPGA | — |
| Logic Elements | 320,000 | 320,000 |
| Hard Processor Subsystem (HPS) | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| HPS Clock Frequency | 1.5 GHz | Up to 1.5 GHz |
| Speed Grade | E4 (-4, mid-tier) | — |
| Temperature Grade | Industrial (-40C to +100C) | — |
| Boîtier | 672-pin FCBGA (F27, 27x27 mm) | 672-pin FCBGA (Flip-Chip BGA), 27 x 27 mm |
| Type de montage | Surface Mount | Surface Mount |
| Statut RoHS | Compliant | — |
| Lead-Free | Yes | — |
| Niveau MSL | [DATA_NEEDED: MSL rating per JEDEC J-STD-020] | — |
| Process Technology | 20 nm | 20 nm |
| Transceivers | Up to 24 channels, up to 14.1 Gbps (family-level) | — |
| DSP Blocks | Hardened floating-point DSP (family-level) | — |
| Memory Interfaces | DDR3 / DDR4 with hard controllers (family-level) | — |
| Configuration Method | JTAG, ASx4, FPP (family-level) | — |
| Manufacturer | — | Intel (formerly Altera) |
| Series | — | Arria 10 SX |
| Device Family | — | Arria 10 SX SoC FPGA |
| Hard Processor System | — | Dual-core ARM Cortex-A9 MPCore with CoreSight |
| Core Voltage (typ.) | — | 0.9 V |
| Terminal Form | — | Ball |
| Number of Terminals | — | 672 |
| Operating Temperature Grade | — | Industrial (-40C to +100C junction) |
| Compliance / Lead-Free | — | RoHS compliant, lead-free |
| Statut du cycle de vie | — | Active |
| FPGA Architecture | — | SRAM-based, volatile configuration |