10AS057K2F35E1HG vs 10AS057K2F35E2LG Comparaison
Comparaison détaillée côte à côte de 10AS057K2F35E1HG par Intel et 10AS057K2F35E2LG par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | 10AS057K2F35E1HG | 10AS057K2F35E2LG |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $1 995,00 | $3 450,00 |
| Family | Arria 10 SX | Arria 10 SX SoC FPGA |
| Logic Elements | 570,000 | 570,000 |
| Adaptive Logic Modules (ALM) | [DATA_NEEDED: ALM count] | — |
| Embedded Memory | 29.4 Mbits (M20K + MLAB) | — |
| DSP Blocks (18x19 Multipliers) | 1,566 | — |
| Maximum User I/O Pins | [DATA_NEEDED: max user I/O] | — |
| Hard Processor System | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| HPS Maximum Frequency | 1.5 GHz | — |
| Transceivers | 24 (up to 17.4 Gbps) | Up to 24 channels, up to 17.4 Gbps |
| PCIe Hard IP | Gen2/Gen3 x8 | Gen3 x4 (rootport/endpoint) |
| Memory Interfaces (FPGA side) | DDR4, DDR3, LPDDR3, QDR IV, RLDRAM 3 | — |
| Memory Interfaces (HPS side) | DDR4, DDR3, LPDDR3 | — |
| Boîtier | 1152-ball FC-BGA (F35), 35x35 mm | 1152-ball FCBGA, 35 mm x 35 mm, 1.0 mm pitch |
| Process Technology | 20 nm TSMC | — |
| Operating Temperature Grade | Industrial | — |
| Statut RoHS | Compliant | Compliant |
| Supply Voltage (Core) | [DATA_NEEDED: Vcore] | — |
| Process Node | — | TSMC 20 nm |
| HPS Cores | — | Dual ARM Cortex-A9 MPCore with CoreSight |
| HPS Max Frequency | — | 1.5 GHz |
| DSP Blocks | — | [DATA_NEEDED: 18x19 multiplier count] |
| Embedded Memory (M20K) | — | [DATA_NEEDED: M20K block count and total bits] |
| User I/Os | — | 396 |
| Speed Grade | — | E2 (commercial/extended) |
| Température de fonctionnement | — | -40C to +100C (extended-industrial screening) |
| Configuration | — | SRAM-based, partial reconfiguration, SEU mitigation, ECC |
| Memory Interfaces | — | DDR3/DDR4 with hard PHY (HPS + FPGA) |
| Lead-Free | — | Yes |