10AS057K2F35E1HG vs 10AS057K2F35E2LG Comparação
Comparação detalhada lado a lado de 10AS057K2F35E1HG por Intel e 10AS057K2F35E2LG por Intel. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | 10AS057K2F35E1HG | 10AS057K2F35E2LG |
|---|---|---|
| Marca | Intel | Intel |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Ativo | Ativo |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $1.995,00 | $3.450,00 |
| Family | Arria 10 SX | Arria 10 SX SoC FPGA |
| Logic Elements | 570,000 | 570,000 |
| Adaptive Logic Modules (ALM) | [DATA_NEEDED: ALM count] | — |
| Embedded Memory | 29.4 Mbits (M20K + MLAB) | — |
| DSP Blocks (18x19 Multipliers) | 1,566 | — |
| Maximum User I/O Pins | [DATA_NEEDED: max user I/O] | — |
| Hard Processor System | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| HPS Maximum Frequency | 1.5 GHz | — |
| Transceivers | 24 (up to 17.4 Gbps) | Up to 24 channels, up to 17.4 Gbps |
| PCIe Hard IP | Gen2/Gen3 x8 | Gen3 x4 (rootport/endpoint) |
| Memory Interfaces (FPGA side) | DDR4, DDR3, LPDDR3, QDR IV, RLDRAM 3 | — |
| Memory Interfaces (HPS side) | DDR4, DDR3, LPDDR3 | — |
| Encapsulamento | 1152-ball FC-BGA (F35), 35x35 mm | 1152-ball FCBGA, 35 mm x 35 mm, 1.0 mm pitch |
| Process Technology | 20 nm TSMC | — |
| Operating Temperature Grade | Industrial | — |
| Status RoHS | Compliant | Compliant |
| Supply Voltage (Core) | [DATA_NEEDED: Vcore] | — |
| Process Node | — | TSMC 20 nm |
| HPS Cores | — | Dual ARM Cortex-A9 MPCore with CoreSight |
| HPS Max Frequency | — | 1.5 GHz |
| DSP Blocks | — | [DATA_NEEDED: 18x19 multiplier count] |
| Embedded Memory (M20K) | — | [DATA_NEEDED: M20K block count and total bits] |
| User I/Os | — | 396 |
| Speed Grade | — | E2 (commercial/extended) |
| Temperatura de operação | — | -40C to +100C (extended-industrial screening) |
| Configuration | — | SRAM-based, partial reconfiguration, SEU mitigation, ECC |
| Memory Interfaces | — | DDR3/DDR4 with hard PHY (HPS + FPGA) |
| Lead-Free | — | Yes |