5CSEBA2U19C6N vs 5CSEBA6U19C6N Comparaison
Comparaison détaillée côte à côte de 5CSEBA2U19C6N par Intel et 5CSEBA6U19C6N par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | 5CSEBA2U19C6N | 5CSEBA6U19C6N |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $74,60 | $194,15 |
| Family | Cyclone V SE SoC FPGA | — |
| Logic Elements | 25 K | 110K |
| Hard Processor System | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| HPS Maximum Clock Frequency | 925 MHz | — |
| DSP Blocks | Variable-precision DSP | Variable-precision DSP |
| Boîtier | 484-pin UBGA (19x19 mm) | 484-UBGA (UBGА, 19x19 mm) |
| Type de montage | Surface Mount | Surface Mount (BGA) |
| Operating Temperature Grade | Commercial (other) | — |
| Memory Interfaces | DDR2, DDR3, LPDDR2 with ECC | — |
| HPS Peripherals | GbE, USB 2.0 OTG, SATA, CAN, UART, SPI, I2C, SD/SDIO/MMC | — |
| L2 Cache | 512 KB shared | — |
| L1 Cache per Core | 32 KB I-cache + 32 KB D-cache | — |
| FPGA-to-HPS Bridges | AXI-32/AXI-64, FPGA-to-SDRAM ports | — |
| Process Technology | TSMC 28 nm low-power | TSMC 28 nm low-power |
| Statut RoHS | Compliant | Compliant (per Altera/Intel product page) |
| Manufacturer | — | Altera (Intel) |
| Series | — | Cyclone V SE SoC FPGA |
| Device Variant | — | 5CSEA6 (U19 package) |
| HPS Architecture | — | Dual ARM Cortex-A9 MPCore with CoreSight |
| HPS Frequency | — | 925 MHz |
| FPGA Speed Grade | — | -6 (industrial) |
| Nombre de broches | — | 484 |
| User I/O | — | 66 (per Heisener) / configurable LVDS/LVCMOS |
| Hard IP Blocks | — | PCIe Gen2, multi-port memory controller, ARM Cortex-A9 HPS |
| Memory | — | Embedded M10K blocks |
| Température de fonctionnement | — | -40C to +100C (industrial) |
| Niveau MSL | — | 3 (per BGA package) |