5CSEBA4U19I7S-N vs 5CSEBA4U19I7SN Comparaison
Comparaison détaillée côte à côte de 5CSEBA4U19I7S-N par Intel et 5CSEBA4U19I7SN par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Intel
5CSEBA4U19I7S-N - Cyclone V SE SoC FPGA, 40K LE, ARM Cortex-A9 | Intel
5CSEBA4U19I7S-N ✓ ActifComparaison des spécifications
| Paramètre | 5CSEBA4U19I7S-N | 5CSEBA4U19I7SN |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $295,40 | $145,00 |
| Family | Cyclone V SE | — |
| Device Type | SoC FPGA with ARM Cortex-A9 MPCore + CoreSight | — |
| Logic Elements | 40,000 | 40,000 |
| Process Technology | 28 nm TSMC low-power | — |
| Core Voltage | 1.1 V | — |
| Hard Processor System Cores | 1 x ARM Cortex-A9 MPCore | — |
| Maximum HPS Clock Frequency | 800 MHz | — |
| Boîtier | 484-ball UFBGA (19x19 mm) | 484-pin UBG A (19x19 mm) |
| Type de montage | Surface Mount | Surface Mount |
| Maximum Seated Height | 1.9 mm | — |
| Operating Temperature Grade | Industrial (-40C to +100C Tj) | — |
| Speed Grade | 7 | — |
| Supply Type | Tray | — |
| Statut RoHS | Compliant | Compliant |
| Lead-Free | Yes | — |
| Series | — | Cyclone V SE SoC FPGA |
| Device Family | — | Cyclone V |
| Hard Processor System (HPS) | — | Single ARM Cortex-A9 MPCore with CoreSight |
| HPS Maximum Frequency | — | 800 MHz |
| Température de fonctionnement | — | -40C to +100C (Industrial) |
| Process Node | — | 28 nm low-power |
| Supply Voltage (Core) | — | 1.1 V (typical) |
| I/O Standards Supported | — | LVTTL, LVCMOS, LVDS, SSTL, HSTL (Cyclone V I/O family) |
| Embedded Memory | — | [DATA_NEEDED: total Kbits of M9K blocks] |
| 18x18 Hardware Multipliers | — | [DATA_NEEDED: count] |
| PLLs | — | [DATA_NEEDED: count] |
| Transceivers | — | Not applicable (SE family, transceiver-less) |
| PCI Express Hard IP | — | Gen1 capable (rootport/endpoint) |
| DDR Memory Support | — | DDR2/DDR3/LPDDR2 via HPS and FPGA fabric |