5CSEBA4U19I7S-N vs 5CSEBA4U19I7SN Vergleich
Detaillierter Direktvergleich von 5CSEBA4U19I7S-N von Intel und 5CSEBA4U19I7SN von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
5CSEBA4U19I7S-N - Cyclone V SE SoC FPGA, 40K LE, ARM Cortex-A9 | Intel
5CSEBA4U19I7S-N ✓ AktivSpezifikationsvergleich
| Parameter | 5CSEBA4U19I7S-N | 5CSEBA4U19I7SN |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $295,40 | $145,00 |
| Family | Cyclone V SE | — |
| Device Type | SoC FPGA with ARM Cortex-A9 MPCore + CoreSight | — |
| Logic Elements | 40,000 | 40,000 |
| Process Technology | 28 nm TSMC low-power | — |
| Core Voltage | 1.1 V | — |
| Hard Processor System Cores | 1 x ARM Cortex-A9 MPCore | — |
| Maximum HPS Clock Frequency | 800 MHz | — |
| Gehäuse | 484-ball UFBGA (19x19 mm) | 484-pin UBG A (19x19 mm) |
| Montageart | Surface Mount | Surface Mount |
| Maximum Seated Height | 1.9 mm | — |
| Operating Temperature Grade | Industrial (-40C to +100C Tj) | — |
| Speed Grade | 7 | — |
| Supply Type | Tray | — |
| RoHS-Status | Compliant | Compliant |
| Lead-Free | Yes | — |
| Series | — | Cyclone V SE SoC FPGA |
| Device Family | — | Cyclone V |
| Hard Processor System (HPS) | — | Single ARM Cortex-A9 MPCore with CoreSight |
| HPS Maximum Frequency | — | 800 MHz |
| Betriebstemperatur | — | -40C to +100C (Industrial) |
| Process Node | — | 28 nm low-power |
| Supply Voltage (Core) | — | 1.1 V (typical) |
| I/O Standards Supported | — | LVTTL, LVCMOS, LVDS, SSTL, HSTL (Cyclone V I/O family) |
| Embedded Memory | — | [DATA_NEEDED: total Kbits of M9K blocks] |
| 18x18 Hardware Multipliers | — | [DATA_NEEDED: count] |
| PLLs | — | [DATA_NEEDED: count] |
| Transceivers | — | Not applicable (SE family, transceiver-less) |
| PCI Express Hard IP | — | Gen1 capable (rootport/endpoint) |
| DDR Memory Support | — | DDR2/DDR3/LPDDR2 via HPS and FPGA fabric |