5CSEBA4U23C8N vs 5CSEBA4U23I7LN Comparaison
Comparaison détaillée côte à côte de 5CSEBA4U23C8N par Intel et 5CSEBA4U23I7LN par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Intel
5CSEBA4U23C8N - Cyclone V SE SoC FPGA, 40K LE, Dual ARM Cortex-A9 | Intel
5CSEBA4U23C8N ✓ ActifComparaison des spécifications
| Paramètre | 5CSEBA4U23C8N | 5CSEBA4U23I7LN |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $138,20 | $99,75 |
| Family | Cyclone V SE SoC FPGA | Cyclone V SE SoC FPGA |
| Logic Elements (LE) | 40,000 | — |
| Processor Core | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| Maximum HPS Frequency | 600 MHz | — |
| Embedded Memory | [DATA_NEEDED: total Kbits] | [DATA_NEEDED: exact embedded memory size in bits] |
| DSP Blocks | [DATA_NEEDED: variable-precision DSP count] | — |
| Multipliers | 18x18 dedicated multipliers | — |
| Maximum User I/O | 188 | — |
| Boîtier | 672-pin UBGA (UBGA-672, 23x23 mm) | 672-pin UBGA (23x23 mm) |
| Process Technology | TSMC 28 nm low-power | 28nm TSMC low-power |
| HPS Peripherals | Gigabit Ethernet, USB 2.0 OTG, CAN, UART, SPI, I2C, NAND, SDXC | — |
| Memory Controller (HPS) | DDR3/DDR3L/LPDDR2 with hard PHY | — |
| Température de fonctionnement | [DATA_NEEDED: industrial Tj range] | -40C to +100C (Industrial) |
| Type de montage | Surface Mount (BGA) | Surface Mount |
| Statut RoHS | Compliant | Compliant |
| Lead-Free | Yes | Yes |
| Logic Elements | — | 40,000 |
| Processor Cores | — | Dual ARM Cortex-A9 MPCore |
| Processor Clock Speed | — | 925 MHz |
| DSP Blocks (18x18 multipliers) | — | [DATA_NEEDED: exact multiplier count] |
| Transceivers | — | 3.125 Gbps (per Cyclone V family) |
| External Memory Interface | — | DDR3, DDR2, LPDDR2 (controller integrated in HPS + soft IP in FPGA fabric) |
| Niveau MSL | — | 3 |
| Sans halogène | — | [DATA_NEEDED] |
| Number of GPIOs | — | [DATA_NEEDED: per device variant] |
| Number of PLLs | — | [DATA_NEEDED: per device variant] |