5CSEBA5U19A7N vs 5CSEBA5U19C7N Comparaison
Comparaison détaillée côte à côte de 5CSEBA5U19A7N par Intel et 5CSEBA5U19C7N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Intel
5CSEBA5U19A7N - Cyclone V SE SoC FPGA, 85K LE, Dual ARM Cortex-A9 | Intel
5CSEBA5U19A7N ✓ ActifComparaison des spécifications
| Paramètre | 5CSEBA5U19A7N | 5CSEBA5U19C7N |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $152,40 | $99,20 |
| Family | Cyclone V SE SoC FPGA | Cyclone V SE SoC FPGA |
| Logic Elements | 85,000 | 85,000 |
| Process Technology | 28 nm low-power | — |
| Hard Processor System (HPS) | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| HPS Maximum Frequency | 700 MHz | 800 MHz per core |
| Boîtier | 484-pin UBG A (19x19 mm) | 484-UBGA (UBGAmobile, 19x19 mm) |
| Type de montage | Surface Mount (BGA) | Surface Mount (BGA) |
| Supply Voltage (Core) | 1.1 V | 1.1 V typical |
| Operating Temperature Grade | Automotive (AEC-Q100) -40C to +125C | — |
| I/O Count | 66 (per source listing) | — |
| Memory Interface | DDR3 controller in HPS; external memory interface in FPGA fabric | — |
| DSP Blocks | Variable-precision DSP blocks | Variable-precision, 18x18 / 27x27 multipliers |
| Configuration / Boot Modes | NAND, QSPI, SD/MMC | — |
| Statut RoHS | Compliant (per Ampheo listing) | — |
| Automotive Qualification | AEC-Q100 (Automotive grade, indicated by 'A' in part number) | — |
| Hard Processor System | — | Dual ARM Cortex-A9 MPCore with CoreSight |
| Température de fonctionnement | — | 0C to +85C (commercial, junction) |
| Speed Grade | — | -7 (standard) |
| Process Node | — | 28 nm low-power (TSMC) |
| Embedded Memory | — | M10K + MLAB blocks, ~4,450 Kbits total |
| HPS Peripherals | — | EMAC, USB 2.0 OTG, NAND, DDR3, SPI, QSPI, I2C, UART |
| RoHS / Pb-free | — | Yes |
| Configuration Memory | — | External (active serial via HPS or FPGA) |
| Niveau MSL | — | 3 (per JEDEC J-STD-020, reflow 260C) |
| Block Pins (User I/O) | — | Approximately 66 user I/O pins |