5CSXFC6C6U23C6N vs 5CSXFC6C6U23C8N Comparaison
Comparaison détaillée côte à côte de 5CSXFC6C6U23C6N par Intel et 5CSXFC6C6U23C8N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Intel
5CSXFC6C6U23C8N - Cyclone V SX SoC FPGA, 110K LE, ARM Cortex-A9 | Intel
5CSXFC6C6U23C8N ✓ ActifComparaison des spécifications
| Paramètre | 5CSXFC6C6U23C6N | 5CSXFC6C6U23C8N |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $285,00 | $445,00 |
| Series | Cyclone V SX SoC FPGA | Cyclone V SX |
| Family | Cyclone V SX | Cyclone V SX (SoC FPGA) |
| Logic Elements | 110,000 | 110,000 |
| Processor Core | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| Maximum Fabric Frequency | 925 MHz | — |
| Process Technology | 28 nm low-power | 28 nm low-power (TSMC) |
| Core Supply Voltage | 1.1 V | — |
| Boîtier | 672-UBGA (UFBGA) 23x23 mm | 672-pin UFBGA (UBGA), 23x23 mm |
| Type de montage | Surface Mount (BGA) | Surface Mount (BGA) |
| Température de fonctionnement | 0 C to +85 C (commercial) | -40C to +100C (industrial grade, code C) |
| Number of I/O | 145 (per JAK Electronics comparison) | — |
| Embedded Memory | approximately 4,160 Kbits | M10K blocks (total Kbits [DATA_NEEDED: total embedded memory Kbits]) |
| DSP Blocks | approximately 112 | Variable-precision DSP (number not specified in retrieved data) |
| Statut RoHS | Compliant | Compliant |
| Niveau MSL | 3 (per typical BGA handling) | 3 (per JEDEC J-STD-020, typical for large BGA) |
| Architecture | — | MCU + FPGA (Hard Processor System + FPGA fabric) |
| Core Voltage | — | 1.1 V |
| Hard Processor System (HPS) | — | Dual-core ARM Cortex-A9 MPCore with CoreSight |
| Processor Maximum Frequency | — | 600 MHz |
| HPS L1 Cache | — | 32 KB instruction + 32 KB data per core |
| HPS L2 Cache | — | 512 KB shared |
| Transceivers | — | Up to 3.125 Gbps integrated transceivers |
| Maximum User I/O | — | 145 user I/O (per DigChip summary; full count per package [DATA_NEEDED: package pinout max user I/O]) |
| Memory Controller | — | Hard controller supporting DDR2, DDR3, LPDDR2 |
| Lead-Free / Halogen-Free | — | Yes (lead-free BGA; halogen status [DATA_NEEDED: halogen-free yes/no]) |
| Speed Grade | — | C8 (commercial speed grade 8) |
| Lifecycle | — | Active (Cyclone V family in production) |