5M240ZT144I5N vs 5M1270ZT144C5N Comparaison
Comparaison détaillée côte à côte de 5M240ZT144I5N par Intel et 5M1270ZT144C5N par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
5M1270ZT144C5N - MAX V CPLD 980 Macrocells 114 I/O TQFP-144 | Intel / Altera
5M1270ZT144C5N ✓ ActifComparaison des spécifications
| Paramètre | 5M240ZT144I5N | 5M1270ZT144C5N |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $13,80 | $12,45 |
| Family | MAX V | — |
| Device Logic Elements | 240 LE | — |
| Number of Logic Array Blocks | 12 LAB | — |
| Maximum User I/O Pins | 114 | — |
| User Flash Memory (UFM) | 8 Kbits | 8 Kbits |
| Internal Core Voltage | 1.8 V | — |
| I/O Bank Voltage | 1.2 V to 3.3 V (multi-voltage) | — |
| Speed Grade | I5 (industrial, -40 C to +100 C) | — |
| Boîtier | TQFP-144 (T144) 22x22 mm | TQFP-144 (22 x 22 mm, 0.5 mm pitch) |
| Type de montage | Surface Mount | Surface Mount |
| Température de fonctionnement | -40 C to +100 C (industrial) | 0 C to +85 C (commercial grade) |
| Configuration Memory | Non-volatile (flash) | Flash (non-volatile, in-system programmable) |
| Programming Interface | JTAG (IEEE 1149.1) | JTAG in-system programmable (Altera Quartus II) |
| Standby Current (typical) | <1 mA | — |
| Statut RoHS | Compliant | Compliant |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Series | — | MAX V |
| Logic Elements | — | 1270 |
| Macrocells | — | 980 |
| User I/Os | — | 114 |
| Maximum Internal Frequency | — | 118.3 MHz |
| Pin-to-Pin Propagation Delay (tPD) | — | 6.2 ns |
| Internal Frequency (typical) | — | 201 MHz |
| VCCINT (Core Supply) | — | 1.71 V to 1.89 V |
| VCCIO (I/O Supply, per bank) | — | 1.2 V to 3.3 V |
| Number of I/O Banks | — | 4 |
| Supported I/O Standards | — | LVCMOS, LVTTL, PCI up to 3.3 V, 1.2 V to 3.3 V LVCMOS on JTAG pins |
| JTAG Interface | — | IEEE 1149.1 (TMS, TDI, TDO, TCK in Bank 1) |
| Program/Erase Cycles | — | Up to 100,000 |