A3PE3000-1FGG896 vs A3PE3000L-FGG896M Comparaison
Comparaison détaillée côte à côte de A3PE3000-1FGG896 par Microchip Technology et A3PE3000L-FGG896M par Microchip Technology. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Microchip Technology
A3PE3000-1FGG896 - ProASIC3E Flash FPGA 3M Gates 620 I/O | Microchip
A3PE3000-1FGG896 ✓ ActifMicrochip Technology
A3PE3000L-FGG896M - 3M-Gate Low-Power Flash FPGA | Microchip
A3PE3000L-FGG896M ✓ ActifComparaison des spécifications
| Paramètre | A3PE3000-1FGG896 | A3PE3000L-FGG896M |
|---|---|---|
| Marque | Microchip Technology | Microchip Technology |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $0,00 | $0,00 |
| Family | ProASIC3E (Flash FPGA) | ProASIC3L (Flash-based FPGA) |
| System Gates | 3,000,000 | 3,000,000 |
| Logic Cells | 75,264 | 75,264 |
| User I/O | 620 | — |
| Speed Grade | -1 | — |
| Boîtier | 896-ball FBGA (FGG896) | 896-ball FBGA (FGG896), 1 mm pitch |
| Technology | Nonvolatile flash, CMOS | — |
| Configuration | Single-chip, Instant On (on-chip flash) | Non-volatile flash, live-at-power-up Level 0, single-chip |
| Reprogrammability | Yes (in-system reprogrammable flash fabric) | — |
| Type de montage | Surface Mount | Surface Mount |
| Core Voltage | [DATA_NEEDED: core voltage] | 1.2 V to 1.5 V |
| Température de fonctionnement | [DATA_NEEDED: operating temperature range] | 0 to 70 C |
| Embedded Memory | [DATA_NEEDED: embedded block RAM capacity] | — |
| Lead Free | Yes (LEAD FREE per distributor listing) | — |
| Statut RoHS | Compliant | — |
| Niveau MSL | [DATA_NEEDED: moisture sensitivity level] | — |
| Country of Origin | South Korea (per MicrochipDirect for A3PE3000-1FG896 family variant) | — |
| User I/Os | — | Up to 616 (620 per DigiKey listing) |
| Embedded SRAM | — | 504 kbits true dual-port |
| Process Technology | — | 130-nm, 7-layer metal (6 copper), flash-based CMOS |
| Tension d'alimentation | — | 1.5 V |
| Logic Family | — | CMOS |
| Low-Power Feature | — | Flash*Freeze technology |
| Boundary Scan | — | IEEE 1149.1 (JTAG) |
| Input Features | — | Schmitt trigger option on single-ended inputs; weak pull-up/pull-down |