ADC1112D125HN-C18 vs ADC1113D125HN-C1 Comparaison
Comparaison détaillée côte à côte de ADC1112D125HN-C18 par Renesas Electronics et ADC1113D125HN-C1 par Renesas Electronics. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Renesas Electronics
ADC1112D125HN-C18 - Dual 11-bit 125MSPS ADC, LVDS/CMOS | Renesas
ADC1112D125HN-C18 ✓ ActifRenesas Electronics
ADC1113D125HN-C1 - Dual 11-bit 125 Msps ADC, JESD204A | Renesas
ADC1113D125HN-C1 ✓ ActifComparaison des spécifications
| Paramètre | ADC1112D125HN-C18 | ADC1113D125HN-C1 |
|---|---|---|
| Marque | Renesas Electronics | Renesas Electronics |
| Catégorie | ADC/DAC | ADC/DAC |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $9,48 | $15,20 |
| Résolution | 11-bit | 11 bit |
| Number of Channels | 2 (dual, simultaneous sampling) | 2 (dual, simultaneous sampling) |
| Sample Rate (Max) | 125 Msps | — |
| Analog Supply Voltage (AVDD) | 3.0 V to 3.6 V | — |
| Digital I/O Supply (OVDD) | 1.8 V to 3.3 V | — |
| Output Interface | CMOS or LVDS DDR (selectable) | — |
| Input Type | Single-ended analog inputs (per channel) | — |
| Reference | Internal programmable (0-6 dB in 1 dB steps) or external | — |
| Control Interface | SPI (3-wire, mode configuration) | — |
| Power-Down Mode | Yes, per-channel via SPI | — |
| Boîtier | HVQFN-64 (8x8 mm with exposed thermal pad) | 56-VFQFN (HVQFN-56) with exposed pad, 9 mm x 9 mm, 0.85 mm height (SOT804-3) |
| Type de montage | Surface Mount | Surface Mount |
| Plage de température de fonctionnement | -40 C to +85 C | [DATA_NEEDED: operating temperature range] |
| Niveau MSL | 3 (168 hours) | [DATA_NEEDED: moisture sensitivity level] |
| Statut RoHS | Compliant | Compliant (assumed from VFQFN package; verify against part declaration) |
| Sample Rate | — | 125 Msps per channel |
| Architecture | — | Pipelined, multi-bit per stage |
| Digital Output Interface | — | JESD204A, serial (CMOS or LVDS DDR) |
| Analog Input | — | Differential, on-chip track-and-hold |
| Supply Voltage (analog) | — | [DATA_NEEDED: AVDD] |
| Supply Voltage (digital) | — | [DATA_NEEDED: DVDD] |
| Power Consumption | — | [DATA_NEEDED: total power at 125 Msps] |
| INL (typical) | — | [DATA_NEEDED: integral non-linearity] |
| DNL (typical) | — | [DATA_NEEDED: differential non-linearity] |
| SNR | — | [DATA_NEEDED: signal-to-noise ratio] |
| SFDR | — | [DATA_NEEDED: spurious-free dynamic range] |
| Input Bandwidth | — | [DATA_NEEDED: analog input bandwidth] |
| Configuration | — | SPI serial control port |