EP1810GM883 vs EP1810JC-25 Comparaison
Comparaison détaillée côte à côte de EP1810GM883 par Altera et EP1810JC-25 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP1810GM883 | EP1810JC-25 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $175,00 | $6,80 |
| Family | Classic EPLD (EP1810 series) | Altera/Intel Classic EPLD (EP1810 series) |
| Device Type | UV-Erasable Programmable Logic Device (EPLD) | — |
| Macrocells | 48 | 48 |
| Dedicated Inputs | 12 | 12 |
| User I/O Pins | 48 | — |
| Total Terminals | 68 | — |
| Global Clocks | 4 | — |
| Supply Voltage (Vcc) | 4.5 V to 5.5 V (nominal 5 V) | — |
| Propagation Delay (tpd) | 45 ns (max) | — |
| Maximum Toggle Frequency (fmax) | [DATA_NEEDED: fmax value not in source data; Classic EPLD family typical 35-80 MHz depending on grade] | — |
| Process Technology | CMOS, UV-erasable | — |
| Boîtier | 68-Pin Ceramic Pin Grid Array (PGA) | 28-pin ceramic DIP (J) with quartz window |
| Température de fonctionnement | -55C to +125C (MIL-STD-883 Class B) | -40 °C to 85 °C (industrial, per distributor listings) |
| Screening | MIL-STD-883 Class B (suffix '883' denotes MIL processing) | — |
| Type de montage | Through-Hole (PGA socket) | Through-hole |
| Statut RoHS | [DATA_NEEDED: hermetic ceramic PGA is typically non-RoHS due to lead-bearing solder/finish; not confirmed in source data] | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free | [DATA_NEEDED: military 883B screened parts commonly use SnPb finish] | — |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Propagation Delay (tPD) | — | 25 ns |
| Maximum Toggle Frequency | — | [DATA_NEEDED: max fMAX] |
| Input Lines | — | 60 (including I/O) |
| I/O Lines | — | 48 |
| External Clock Inputs | — | 4 |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Technology | — | CMOS, UV-erasable (windowed ceramic DIP) |
| Erasure Method | — | UV light (windowed package) |
| Statut du cycle de vie | — | NRND (Not Recommended for New Designs) |