EP1810GM883 vs EP1810JC-25 비교

다음의 상세 나란히 비교: EP1810GM883 제조: Altera 및 EP1810JC-25 제조: Intel. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.

사양 비교

파라미터 EP1810GM883 EP1810JC-25
브랜드 Altera Intel
카테고리 FPGA & CPLD FPGA & CPLD
수명 주기 상태 Obsolete NRND
재고 상태 In Stock In Stock
단가 (USD) $175.00 $6.80
Family Classic EPLD (EP1810 series) Altera/Intel Classic EPLD (EP1810 series)
Device Type UV-Erasable Programmable Logic Device (EPLD) —
Macrocells 48 48
Dedicated Inputs 12 12
User I/O Pins 48 —
Total Terminals 68 —
Global Clocks 4 —
Supply Voltage (Vcc) 4.5 V to 5.5 V (nominal 5 V) —
Propagation Delay (tpd) 45 ns (max) —
Maximum Toggle Frequency (fmax) [DATA_NEEDED: fmax value not in source data; Classic EPLD family typical 35-80 MHz depending on grade] —
Process Technology CMOS, UV-erasable —
패키지 68-Pin Ceramic Pin Grid Array (PGA) 28-pin ceramic DIP (J) with quartz window
동작 온도 -55C to +125C (MIL-STD-883 Class B) -40 °C to 85 °C (industrial, per distributor listings)
Screening MIL-STD-883 Class B (suffix '883' denotes MIL processing) —
실장 유형 Through-Hole (PGA socket) Through-hole
RoHS 상태 [DATA_NEEDED: hermetic ceramic PGA is typically non-RoHS due to lead-bearing solder/finish; not confirmed in source data] [DATA_NEEDED: RoHS compliance status]
Lead-Free [DATA_NEEDED: military 883B screened parts commonly use SnPb finish] —
Product Type — Classic EPLD (Erasable Programmable Logic Device)
Propagation Delay (tPD) — 25 ns
Maximum Toggle Frequency — [DATA_NEEDED: max fMAX]
Input Lines — 60 (including I/O)
I/O Lines — 48
External Clock Inputs — 4
Supply Voltage (VCC) — 4.75 V to 5.25 V
Technology — CMOS, UV-erasable (windowed ceramic DIP)
Erasure Method — UV light (windowed package)
수명 주기 상태 — NRND (Not Recommended for New Designs)

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