EP1810LC-25 vs EP1810LI-35 Comparaison
Comparaison détaillée côte à côte de EP1810LC-25 par Altera et EP1810LI-35 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP1810LC-25 | EP1810LI-35 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $8,40 | $78,05 |
| Product Family | Altera Classic EPLD | — |
| Part Number | EP1810LC-25 | — |
| Macrocells | 48 | 48 |
| Propagation Delay (tPD) | 25 ns | 35 ns |
| Dedicated Inputs | 12 | — |
| I/O Pins | 48 | — |
| External Clock Inputs | 4 | — |
| Supply Voltage (VCC) | 5 V (TTL-compatible) | — |
| Operating Mode | Turbo-only (no slow-power mode) | — |
| Boîtier | 68-pin JLCC (J-leaded ceramic chip carrier) | 68-pin PLCC (J-Lead, plastic) |
| Package Code | LC = 68-pin JLCC | — |
| Type de montage | Surface Mount | Surface Mount (PLCC socket compatible) |
| Technology | CMOS EPLD (erasable programmable logic device) | CMOS, UV-erasable EPROM configuration cell |
| Programmable Interconnect | Global + Local buses | — |
| Programming Method | Altera Classic programmer + MAX+PLUS II legacy flow | — |
| Statut du cycle de vie | Obsolete (legacy Altera Classic family) | — |
| Statut RoHS | [DATA_NEEDED: RoHS compliance not confirmed in legacy datasheet] | [DATA_NEEDED: RoHS compliance status] |
| Température de fonctionnement | [DATA_NEEDED: temperature grade for LC package] | -40 C to +85 C (industrial, 'I' suffix) |
| Manufacturer | — | Rochester Electronics, LLC (original Altera design) |
| Part Family | — | Altera Classic EPLD |
| Device Type | — | Erasable Programmable Logic Device (EPLD) |
| Speed Grade | — | 35 (slowest in EP1810L family) |
| Pin/Package Code | — | PLCC-68 / PQCC68 |
| Tension d'alimentation | — | 5 V (TTL-compatible I/O) |
| JTAG Boundary Scan | — | IEEE 1149.1 compliant |
| Logic Elements | — | Logic Array Blocks (LABs) connected via Programmable Interconnect Array (PIA) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| Niveau MSL | — | [DATA_NEEDED: MSL rating] |