EP1810LC-25 vs EP1810LI-35 Comparação
Comparação detalhada lado a lado de EP1810LC-25 por Altera e EP1810LI-35 por Altera. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | EP1810LC-25 | EP1810LI-35 |
|---|---|---|
| Marca | Altera | Altera |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Obsolete | Obsolete |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $8,40 | $78,05 |
| Product Family | Altera Classic EPLD | — |
| Part Number | EP1810LC-25 | — |
| Macrocells | 48 | 48 |
| Propagation Delay (tPD) | 25 ns | 35 ns |
| Dedicated Inputs | 12 | — |
| I/O Pins | 48 | — |
| External Clock Inputs | 4 | — |
| Supply Voltage (VCC) | 5 V (TTL-compatible) | — |
| Operating Mode | Turbo-only (no slow-power mode) | — |
| Encapsulamento | 68-pin JLCC (J-leaded ceramic chip carrier) | 68-pin PLCC (J-Lead, plastic) |
| Package Code | LC = 68-pin JLCC | — |
| Tipo de montagem | Surface Mount | Surface Mount (PLCC socket compatible) |
| Technology | CMOS EPLD (erasable programmable logic device) | CMOS, UV-erasable EPROM configuration cell |
| Programmable Interconnect | Global + Local buses | — |
| Programming Method | Altera Classic programmer + MAX+PLUS II legacy flow | — |
| Status do ciclo de vida | Obsolete (legacy Altera Classic family) | — |
| Status RoHS | [DATA_NEEDED: RoHS compliance not confirmed in legacy datasheet] | [DATA_NEEDED: RoHS compliance status] |
| Temperatura de operação | [DATA_NEEDED: temperature grade for LC package] | -40 C to +85 C (industrial, 'I' suffix) |
| Manufacturer | — | Rochester Electronics, LLC (original Altera design) |
| Part Family | — | Altera Classic EPLD |
| Device Type | — | Erasable Programmable Logic Device (EPLD) |
| Speed Grade | — | 35 (slowest in EP1810L family) |
| Pin/Package Code | — | PLCC-68 / PQCC68 |
| Tensão de alimentação | — | 5 V (TTL-compatible I/O) |
| JTAG Boundary Scan | — | IEEE 1149.1 compliant |
| Logic Elements | — | Logic Array Blocks (LABs) connected via Programmable Interconnect Array (PIA) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| Nível MSL | — | [DATA_NEEDED: MSL rating] |