EP1810LC-35 vs EP1810LI-35 Comparaison
Comparaison détaillée côte à côte de EP1810LC-35 par Rochester Electronics et EP1810LI-35 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Rochester Electronics
EP1810LC-35 - 48-Macrocell Classic EPLD, 35ns, PLCC-68 | Rochester/Altera
EP1810LC-35 ⚠ Dernier achatComparaison des spécifications
| Paramètre | EP1810LC-35 | EP1810LI-35 |
|---|---|---|
| Marque | Rochester Electronics | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Dernier achat | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $49,20 | $78,05 |
| Device Type | EPLD (Erasable Programmable Logic Device) | Erasable Programmable Logic Device (EPLD) |
| Series | Classic EP1810 | — |
| Macrocells | 48 | 48 |
| Equivalent Gates | 900 usable / 2100 equivalent | — |
| Maximum Operating Frequency | 28.6 MHz | — |
| Propagation Delay (tpd) | 35 ns (max, '-35' speed grade) | — |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | — |
| Technology | CMOS, UV-erasable EPROM | CMOS, UV-erasable EPROM configuration cell |
| Boîtier | 68-pin PLCC (J-Lead) | 68-pin PLCC (J-Lead, plastic) |
| Type de montage | Surface Mount (socketable) | Surface Mount (PLCC socket compatible) |
| Température de fonctionnement | 0C to +70C (commercial) | -40 C to +85 C (industrial, 'I' suffix) |
| I/O Pins | [DATA_NEEDED: I/O count exact] | — |
| Configuration Method | UV-erase + EPROM programmer | — |
| Programmable Interconnect | Centralized Programmable Interconnect Array (PIA) | — |
| Development Tool (legacy) | MAX+PLUS II / A+PLUS | — |
| Statut RoHS | [DATA_NEEDED] | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free | [DATA_NEEDED] | [DATA_NEEDED: lead-free status] |
| Manufacturer | — | Rochester Electronics, LLC (original Altera design) |
| Part Family | — | Altera Classic EPLD |
| Propagation Delay (tPD) | — | 35 ns |
| Speed Grade | — | 35 (slowest in EP1810L family) |
| Pin/Package Code | — | PLCC-68 / PQCC68 |
| Tension d'alimentation | — | 5 V (TTL-compatible I/O) |
| JTAG Boundary Scan | — | IEEE 1149.1 compliant |
| Logic Elements | — | Logic Array Blocks (LABs) connected via Programmable Interconnect Array (PIA) |
| Niveau MSL | — | [DATA_NEEDED: MSL rating] |