EP1810LC-35T vs EP1810LC-25 Comparaison
Comparaison détaillée côte à côte de EP1810LC-35T par Intel et EP1810LC-25 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP1810LC-35T | EP1810LC-25 |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $115,20 | $8,40 |
| Device Family | EP1810 Classic EPLD | — |
| Product Type | Erasable Programmable Logic Device (EPLD) | — |
| Usable Gates | 900 | — |
| Macro Cells | 48 | — |
| Pin-to-Pin Delay (tpd) | 35 ns | — |
| Maximum Frequency (fmax) | 28.6 MHz | — |
| Supply Voltage (Vcc) | 5 V | — |
| Technology | CMOS | CMOS EPLD (erasable programmable logic device) |
| Logic Compatibility | 100% TTL emulation | — |
| Boîtier | 68-pin PLCC (Plastic Leaded Chip Carrier) | 68-pin JLCC (J-leaded ceramic chip carrier) |
| Package Suffix | T = Tape and Reel | — |
| Température de fonctionnement | 0 C to +70 C (Commercial) | [DATA_NEEDED: temperature grade for LC package] |
| Type de montage | Surface Mount (PLCC socket or direct solder) | Surface Mount |
| Programming Method | UV-erasable (ceramic) / OTP (plastic); MAX+PLUS II | Altera Classic programmer + MAX+PLUS II legacy flow |
| Statut RoHS | Non-compliant (legacy PLCC product) | [DATA_NEEDED: RoHS compliance not confirmed in legacy datasheet] |
| Logic Family Replacement Target | 74LS low-power Schottky TTL | — |
| Product Family | — | Altera Classic EPLD |
| Part Number | — | EP1810LC-25 |
| Macrocells | — | 48 |
| Propagation Delay (tPD) | — | 25 ns |
| Dedicated Inputs | — | 12 |
| I/O Pins | — | 48 |
| External Clock Inputs | — | 4 |
| Supply Voltage (VCC) | — | 5 V (TTL-compatible) |
| Operating Mode | — | Turbo-only (no slow-power mode) |
| Package Code | — | LC = 68-pin JLCC |
| Programmable Interconnect | — | Global + Local buses |
| Statut du cycle de vie | — | Obsolete (legacy Altera Classic family) |