EP1810LC-35T vs EP1810LC-25 Comparação

Comparação detalhada lado a lado de EP1810LC-35T por Intel e EP1810LC-25 por Altera. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.

Comparação de especificações

Parâmetro EP1810LC-35T EP1810LC-25
Marca Intel Altera
Categoria FPGA & CPLD FPGA & CPLD
Status do ciclo de vida Obsolete Obsolete
Status do estoque In Stock In Stock
Preço unitário (USD) $115,20 $8,40
Device Family EP1810 Classic EPLD —
Product Type Erasable Programmable Logic Device (EPLD) —
Usable Gates 900 —
Macro Cells 48 —
Pin-to-Pin Delay (tpd) 35 ns —
Maximum Frequency (fmax) 28.6 MHz —
Supply Voltage (Vcc) 5 V —
Technology CMOS CMOS EPLD (erasable programmable logic device)
Logic Compatibility 100% TTL emulation —
Encapsulamento 68-pin PLCC (Plastic Leaded Chip Carrier) 68-pin JLCC (J-leaded ceramic chip carrier)
Package Suffix T = Tape and Reel —
Temperatura de operação 0 C to +70 C (Commercial) [DATA_NEEDED: temperature grade for LC package]
Tipo de montagem Surface Mount (PLCC socket or direct solder) Surface Mount
Programming Method UV-erasable (ceramic) / OTP (plastic); MAX+PLUS II Altera Classic programmer + MAX+PLUS II legacy flow
Status RoHS Non-compliant (legacy PLCC product) [DATA_NEEDED: RoHS compliance not confirmed in legacy datasheet]
Logic Family Replacement Target 74LS low-power Schottky TTL —
Product Family — Altera Classic EPLD
Part Number — EP1810LC-25
Macrocells — 48
Propagation Delay (tPD) — 25 ns
Dedicated Inputs — 12
I/O Pins — 48
External Clock Inputs — 4
Supply Voltage (VCC) — 5 V (TTL-compatible)
Operating Mode — Turbo-only (no slow-power mode)
Package Code — LC = 68-pin JLCC
Programmable Interconnect — Global + Local buses
Status do ciclo de vida — Obsolete (legacy Altera Classic family)

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