EP1AGX50DF780C6 vs EP1AGX50DF780I6N Comparaison
Comparaison détaillée côte à côte de EP1AGX50DF780C6 par Intel et EP1AGX50DF780I6N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP1AGX50DF780C6 | EP1AGX50DF780I6N |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $205,00 | $255,00 |
| Family | Arria GX | Arria GX |
| Logic Elements | 50,160 | — |
| Logic Array Blocks (LABs) | 2,508 | 2,508 |
| Embedded Memory (bits) | 2,475,072 | — |
| User I/O Count | 350 | — |
| Boîtier | 780-pin FBGA (FineLine BGA) | 780-pin FBGA (FineLine BGA) |
| Speed Grade | C6 | — |
| Temperature Grade | Commercial (0C to +85C) | — |
| Transceiver Data Rate (max) | Up to 3.125 Gbps | — |
| Hard PCI Express IP | Yes (x1/x4 endpoint and root port, PCIe 1.0) | — |
| Embedded Multipliers | 18x18 multipliers | Yes (DSP blocks, 18x18) |
| Process Technology | 90 nm | CMOS, 1.2V core |
| Configuration Modes | JTAG, Passive Serial (PS), Fast Passive Parallel (FPP) | — |
| Supply Voltage (Core) | 1.2 V | — |
| I/O Standards Supported | LVTTL, LVCMOS, LVDS, SSTL, HSTL, PCI, PCI-X | — |
| Statut RoHS | Non-Compliant (per Besenchips listing - contains lead) | Compliant |
| Logic Elements (LEs) | — | 50,160 |
| User I/O Pins | — | 350 |
| Type de montage | — | Surface Mount |
| Operating Temperature Grade | — | Industrial (I6, -40C to +100C junction) |
| Configuration Mode | — | Serial / Parallel / JTAG |
| Embedded Transceivers | — | Yes (multi-channel, protocol-specific) |
| Embedded Memory | — | [DATA_NEEDED: total Mbits and block size] |
| Niveau MSL | — | [DATA_NEEDED: MSL rating] |
| Lead-Free / Halogen-Free | — | Lead-free per Intel datasheet |
| Tension d'alimentation | — | 1.2V core (with auxiliary rails per datasheet) |