EP1K100FC256-2 vs EP1K100FI256-3 Comparaison
Comparaison détaillée côte à côte de EP1K100FC256-2 par Altera et EP1K100FI256-3 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Intel
EP1K100FI256-3 - 100K-Gate ACEX 1K FPGA, 186 I/O, FBGA-256 | Intel
EP1K100FI256-3 ⚠ Dernier achatComparaison des spécifications
| Paramètre | EP1K100FC256-2 | EP1K100FI256-3 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Dernier achat |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $27,60 | $52,90 |
| Product Family | ACEX-1K | — |
| Product Type | Field Programmable Gate Array (FPGA) | — |
| Equivalent Logic Gates | 257000 | — |
| Logic Elements / Cells | 4992 | — |
| Logic Array Blocks (LABs) | 624 | — |
| Total RAM Bits | 49152 | — |
| User I/O Pins | 186 | 186 |
| Core Supply Voltage | 2.5 V | — |
| Technology | 0.22 um CMOS | — |
| Boîtier | 256-Ball FBGA (256-BGA) | 256-ball FineLine BGA (FBGA-256) |
| Number of Terminals | 256 | — |
| Terminal Form | Ball | — |
| Terminal Pitch | 1.00 mm | — |
| Package Shape | Square | — |
| Speed Grade | -2 | -3 |
| Maximum Internal Frequency | 250 MHz | — |
| Type de montage | Surface Mount | Surface Mount |
| Operating Temperature Grade | Commercial (C suffix); exact min/max [DATA_NEEDED: Operating temperature range] | — |
| Family | — | ACEX 1K |
| Device Logic Elements | — | 4,992 |
| Typical Gate Count | — | 100,000 gates |
| Maximum RAM Bits | — | 49,152 bits |
| Dedicated Inputs | — | 6 |
| Nominal Core Voltage | — | 2.5 V |
| Core Voltage Range | — | 2.375 V to 2.625 V |
| Process Technology | — | 0.22 micron CMOS |
| Plage de température de fonctionnement | — | -40 C to +85 C (Industrial) |
| Configuration Method | — | SRAM-based, JTAG / PS / AS supported |
| Statut RoHS | — | [DATA_NEEDED: RoHS status] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| AEC-Q100 Qualification | — | Not qualified |
| Niveau MSL | — | [DATA_NEEDED: MSL level] |
| JTAG Boundary Scan | — | Yes (IEEE 1149.1) |