EP1M120B484C8A vs EP1M120B484C5 Comparaison
Comparaison détaillée côte à côte de EP1M120B484C8A par Altera et EP1M120B484C5 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP1M120B484C8A | EP1M120B484C5 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $62,00 | $65,00 |
| Family | Mercury (EP1M) | Mercury (EP1M) |
| Logic Elements (approx.) | 120 | — |
| Boîtier | 484-ball FineLine BGA | FineLine BGA-484 (19 mm x 19 mm, 1.0 mm pitch) |
| Nombre de broches | 484 | — |
| Speed Grade | 8 | 5 (slowest) |
| Temperature Grade | Commercial (C) | — |
| Température de fonctionnement | [DATA_NEEDED: full range] | 0C to +85C (commercial) |
| Peak Reflow Temperature | 220 C (per JEDEC J-STD-020) | 220 C |
| Type de montage | Surface Mount (BGA) | Surface Mount |
| Logic Blocks | [DATA_NEEDED: LAB count] | — |
| Embedded Memory | [DATA_NEEDED: RAM bits] | — |
| Maximum User I/O | [DATA_NEEDED: user I/O count] | 303 |
| Supply Voltage Core | [DATA_NEEDED: VCCINT] | — |
| Supply Voltage I/O | [DATA_NEEDED: VCCIO] | — |
| Configuration Method | [DATA_NEEDED: SRAM/serial/etc.] | — |
| Statut RoHS | [DATA_NEEDED: check distributor] | — |
| Niveau MSL | [DATA_NEEDED: per JEDEC J-STD-020] | — |
| Logic Elements | — | 4,800 |
| Typical Gates | — | 120,000 |
| Core Voltage | — | 1.8 V |
| Process Technology | — | 0.18 um CMOS |
| PLLs | — | 4 |
| Embedded RAM Bits | — | 49,152 |
| True LVDS Channels | — | Up to 34 pairs |
| Maximum LVDS Data Rate | — | 840 Mbps per channel |
| Configuration Scheme | — | Passive serial, passive parallel synchronous, passive parallel asynchronous, JTAG |
| Lead-Free / RoHS | — | SnPb ball finish (non-RoHS by default) |
| Multipliers | — | Embedded in system blocks for DSP |