EP1M120F484C5 vs EP1M120B484C5 Comparaison
Comparaison détaillée côte à côte de EP1M120F484C5 par Intel et EP1M120B484C5 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP1M120F484C5 | EP1M120B484C5 |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | NRND | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $110,00 | $65,00 |
| Family | Mercury Device Family | Mercury (EP1M) |
| Device Type | FPGA (Field Programmable Gate Array) | — |
| Logic Array Blocks (LABs) | 480 | — |
| User I/O Count | 303 | — |
| Core Supply Voltage | 1.8 V | — |
| Transceiver Data Rate | 1.25 Gbps (CDR-capable) | — |
| Boîtier | 484-ball FineLine BGA (FBGA-484) | FineLine BGA-484 (19 mm x 19 mm, 1.0 mm pitch) |
| Grade Suffix | C (Commercial, 0 C to +85 C) | — |
| Speed Grade | -5 | 5 (slowest) |
| Architecture | LUT-based, optimized for high performance | — |
| Type de montage | Surface Mount | Surface Mount |
| Température de fonctionnement | 0 C to +85 C (Commercial) | 0C to +85C (commercial) |
| Statut RoHS | [DATA_NEEDED: rohs_status] | — |
| REACH Status | [DATA_NEEDED: reach_status] | — |
| Lead-Free | [DATA_NEEDED: lead_free] | — |
| Sans halogène | [DATA_NEEDED: halogen_free] | — |
| Logic Elements | — | 4,800 |
| Typical Gates | — | 120,000 |
| Maximum User I/O | — | 303 |
| Core Voltage | — | 1.8 V |
| Process Technology | — | 0.18 um CMOS |
| PLLs | — | 4 |
| Embedded RAM Bits | — | 49,152 |
| True LVDS Channels | — | Up to 34 pairs |
| Maximum LVDS Data Rate | — | 840 Mbps per channel |
| Configuration Scheme | — | Passive serial, passive parallel synchronous, passive parallel asynchronous, JTAG |
| Peak Reflow Temperature | — | 220 C |
| Lead-Free / RoHS | — | SnPb ball finish (non-RoHS by default) |
| Multipliers | — | Embedded in system blocks for DSP |