EP1M120F484I6M vs EP1M120F484C7N Comparaison
Comparaison détaillée côte à côte de EP1M120F484I6M par Altera et EP1M120F484C7N par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP1M120F484I6M | EP1M120F484C7N |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | NRND | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $325,00 | $108,00 |
| Family | Mercury (EP1M) | Altera Mercury |
| Logic Elements | 120,000 | — |
| System Gates | 480,000 (typical) | 120,000 |
| LABs / CLBs | 303 | — |
| Flip-Flops | 49,152 | — |
| Embedded Memory (Bits) | 4,800 Kb (480 Kbits) | — |
| Package Type | 484-Ball FCBGA | 484-ball FineLine BGA (FCBGA) |
| Package Code | BGA, 484 balls, Fine-pitch | F484 |
| Package Shape | Square | — |
| Terminal Form | Ball | — |
| Temperature Grade | Industrial | — |
| Speed Grade | -6 (slowest Mercury timing bin) | 7 |
| Tension d'alimentation | 1.5 V core / 3.3 V aux (per Mercury datasheet) | — |
| I/O Standards | LVTTL, LVCMOS, SSTL, HSTL, LVDS | — |
| Clock Management | PLLs (per Mercury family) | — |
| Boundary-Scan | IEEE 1149.1 / JTAG | — |
| Statut RoHS | Compliant (M revision) | — |
| Logic Elements / Cells | — | 4,800 |
| Logic Array Blocks (LABs) | — | 480 |
| Embedded Memory (RAM bits) | — | 49,152 |
| Maximum User I/O Pins | — | 303 |
| Logic Family | — | CMOS |
| Core Supply Voltage | — | 1.8 V |
| Integrated Transceivers | — | Yes - CDR to 1.25 Gbps |
| Température de fonctionnement | — | 0°C to 85°C (Commercial) |
| Temperature Grade Suffix | — | C (Commercial, 0–85°C) |
| RoHS / Lead-Free Suffix | — | N (lead-free) |
| Process Node | — | [DATA_NEEDED: process node] |
| Transceiver Channels | — | [DATA_NEEDED: number of transceiver channels] |