EP1M120F484I6M vs EP1M120F484C7N 比較
詳細な並列比較: EP1M120F484I6M メーカー: Altera および EP1M120F484C7N メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP1M120F484I6M | EP1M120F484C7N |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | NRND | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $325.00 | $108.00 |
| Family | Mercury (EP1M) | Altera Mercury |
| Logic Elements | 120,000 | — |
| System Gates | 480,000 (typical) | 120,000 |
| LABs / CLBs | 303 | — |
| Flip-Flops | 49,152 | — |
| Embedded Memory (Bits) | 4,800 Kb (480 Kbits) | — |
| Package Type | 484-Ball FCBGA | 484-ball FineLine BGA (FCBGA) |
| Package Code | BGA, 484 balls, Fine-pitch | F484 |
| Package Shape | Square | — |
| Terminal Form | Ball | — |
| Temperature Grade | Industrial | — |
| Speed Grade | -6 (slowest Mercury timing bin) | 7 |
| 電源電圧 | 1.5 V core / 3.3 V aux (per Mercury datasheet) | — |
| I/O Standards | LVTTL, LVCMOS, SSTL, HSTL, LVDS | — |
| Clock Management | PLLs (per Mercury family) | — |
| Boundary-Scan | IEEE 1149.1 / JTAG | — |
| RoHS ステータス | Compliant (M revision) | — |
| Logic Elements / Cells | — | 4,800 |
| Logic Array Blocks (LABs) | — | 480 |
| Embedded Memory (RAM bits) | — | 49,152 |
| Maximum User I/O Pins | — | 303 |
| Logic Family | — | CMOS |
| Core Supply Voltage | — | 1.8 V |
| Integrated Transceivers | — | Yes - CDR to 1.25 Gbps |
| 動作温度 | — | 0°C to 85°C (Commercial) |
| Temperature Grade Suffix | — | C (Commercial, 0–85°C) |
| RoHS / Lead-Free Suffix | — | N (lead-free) |
| Process Node | — | [DATA_NEEDED: process node] |
| Transceiver Channels | — | [DATA_NEEDED: number of transceiver channels] |