EP1M120F484I6M vs EP1M120F484C8N Comparaison
Comparaison détaillée côte à côte de EP1M120F484I6M par Altera et EP1M120F484C8N par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP1M120F484I6M | EP1M120F484C8N |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | NRND | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $325,00 | $142,00 |
| Family | Mercury (EP1M) | Mercury (EP1M) |
| Logic Elements | 120,000 | — |
| System Gates | 480,000 (typical) | — |
| LABs / CLBs | 303 | — |
| Flip-Flops | 49,152 | — |
| Embedded Memory (Bits) | 4,800 Kb (480 Kbits) | — |
| Package Type | 484-Ball FCBGA | FINE LINE BGA-484 |
| Package Code | BGA, 484 balls, Fine-pitch | — |
| Package Shape | Square | — |
| Terminal Form | Ball | — |
| Temperature Grade | Industrial | — |
| Speed Grade | -6 (slowest Mercury timing bin) | 8 |
| Tension d'alimentation | 1.5 V core / 3.3 V aux (per Mercury datasheet) | — |
| I/O Standards | LVTTL, LVCMOS, SSTL, HSTL, LVDS | — |
| Clock Management | PLLs (per Mercury family) | — |
| Boundary-Scan | IEEE 1149.1 / JTAG | — |
| Statut RoHS | Compliant (M revision) | [DATA_NEEDED: RoHS compliance] |
| Logic Family | — | CMOS, SRAM-based |
| Number of Logic Elements | — | 49,152 |
| Embedded Memory | — | 4,800 Kbits (M4K blocks) |
| User I/O Pins | — | 303 |
| Terminal Pitch | — | 1.000 mm |
| Type de montage | — | Surface Mount |
| Supply Voltage (Core) | — | 1.8 V nominal (1.71 V min, 1.89 V max) |
| Température de fonctionnement | — | 0 °C to 85 °C (Commercial) |
| Transceivers | — | Up to 8 channels with CDR up to 1.25 Gbps |
| Configuration | — | SRAM, JTAG via Quartus II |
| Niveau MSL | — | [DATA_NEEDED: MSL rating] |