EP1M120F484I6M vs EP1M120F484C8N 比較
詳細な並列比較: EP1M120F484I6M メーカー: Altera および EP1M120F484C8N メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP1M120F484I6M | EP1M120F484C8N |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | NRND | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $325.00 | $142.00 |
| Family | Mercury (EP1M) | Mercury (EP1M) |
| Logic Elements | 120,000 | — |
| System Gates | 480,000 (typical) | — |
| LABs / CLBs | 303 | — |
| Flip-Flops | 49,152 | — |
| Embedded Memory (Bits) | 4,800 Kb (480 Kbits) | — |
| Package Type | 484-Ball FCBGA | FINE LINE BGA-484 |
| Package Code | BGA, 484 balls, Fine-pitch | — |
| Package Shape | Square | — |
| Terminal Form | Ball | — |
| Temperature Grade | Industrial | — |
| Speed Grade | -6 (slowest Mercury timing bin) | 8 |
| 電源電圧 | 1.5 V core / 3.3 V aux (per Mercury datasheet) | — |
| I/O Standards | LVTTL, LVCMOS, SSTL, HSTL, LVDS | — |
| Clock Management | PLLs (per Mercury family) | — |
| Boundary-Scan | IEEE 1149.1 / JTAG | — |
| RoHS ステータス | Compliant (M revision) | [DATA_NEEDED: RoHS compliance] |
| Logic Family | — | CMOS, SRAM-based |
| Number of Logic Elements | — | 49,152 |
| Embedded Memory | — | 4,800 Kbits (M4K blocks) |
| User I/O Pins | — | 303 |
| Terminal Pitch | — | 1.000 mm |
| 実装タイプ | — | Surface Mount |
| Supply Voltage (Core) | — | 1.8 V nominal (1.71 V min, 1.89 V max) |
| 動作温度 | — | 0 °C to 85 °C (Commercial) |
| Transceivers | — | Up to 8 channels with CDR up to 1.25 Gbps |
| Configuration | — | SRAM, JTAG via Quartus II |
| MSLレベル | — | [DATA_NEEDED: MSL rating] |