EP1M350F780I6 vs EP1M350F780I5 Comparaison
Comparaison détaillée côte à côte de EP1M350F780I6 par Altera et EP1M350F780I5 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EP1M350F780I5 - Altera Mercury Enhanced Configuration Device, 780-pin FBGA | Intel
EP1M350F780I5 NrndComparaison des spécifications
| Paramètre | EP1M350F780I6 | EP1M350F780I5 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $210,00 | $178,00 |
| Family | Mercury (PLD) | — |
| Logic Cells | 14,400 | — |
| Equivalent Gates | 350,000 | — |
| User I/Os | 486 | — |
| Embedded Memory (bits) | 114,688 | — |
| Core Supply Voltage | 1.8 V | — |
| Boîtier | 780-ball FC-FBGA (Fine-line) | 780-ball FineLine BGA (F780) |
| Température de fonctionnement | 0 C to 85 C (Industrial) | — |
| Process Technology | CMOS | — |
| Multi-Gigabit Transceivers | Up to 1.25 Gbps with embedded CDR | — |
| Configuration | JTAG (IEEE 1149.1) / Active Serial (EPC) | — |
| LAB Count | 1,440 (per Mouser listing) | — |
| Type de montage | Surface Mount | — |
| Niveau MSL | [DATA_NEEDED: MSL rating] | — |
| Statut RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Device Family | — | Altera Mercury (EP1M) Enhanced Configuration Device |
| Fonction | — | FPGA configuration PROM with integrated controller |
| Storage Density Code | — | 350 (high-density) |
| Supported Configuration Schemes | — | Passive Serial, Active Serial, Fast Passive Parallel |
| Internal Architecture | — | Configuration controller + flash memory array |
| Programming Method | — | In-system programmable via Altera Quartus / JTAG |
| Temperature Grade (suffix "I") | — | Industrial |
| Speed Grade | — | 5 |
| Target FPGA Compatibility | — | Altera APEX 20K, APEX II, Mercury, Stratix-class high-density FPGAs |
| JTAG Support | — | Yes (IEEE 1149.1 boundary scan) |
| Cascade / Multi-FPGA Support | — | Yes, supports daisy-chained multi-FPGA boot |
| Read-Back | — | Yes |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |