EP1S10F672C7N vs EP1S10F672I7 Comparaison
Comparaison détaillée côte à côte de EP1S10F672C7N par Altera et EP1S10F672I7 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP1S10F672C7N | EP1S10F672I7 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Dernier achat |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $171,00 | $124,75 |
| Series | Stratix | — |
| Logic Elements / Cells | 10,570 | — |
| Number of LABs/CLBs | 1,057 | — |
| Total RAM Bits | 920,448 | — |
| Number of User I/Os | 345 | — |
| Number of Gates | [DATA_NEEDED: total gate count] | — |
| DSP Blocks | 6 | Yes (dedicated hardware multipliers) |
| Package Type | 672-BBGA (FBGA) 35 x 35 mm, 1.27 mm pitch | — |
| Type de montage | Surface Mount | Surface Mount (BGA) |
| Process Technology | 130 nm CMOS | 0.13 um CMOS |
| Core Voltage | 1.5 V | — |
| Maximum Operating Frequency | 420.17 MHz | — |
| Température de fonctionnement | 0C to +85C (Commercial) | 0 C to +85 C (industrial grade, I7) |
| Configuration Method | SRAM, JTAG, passive/active serial/parallel | JTAG / serial / parallel PROM |
| Statut RoHS | [DATA_NEEDED: RoHS compliance] | unknown - verify per lot |
| Niveau MSL | [DATA_NEEDED: MSL moisture sensitivity level] | — |
| Family | — | Stratix |
| Logic Elements | — | 10,570 |
| User I/O Pins | — | 345 |
| Boîtier | — | FBGA-672, 35 x 35 mm, 1.27 mm pitch |
| Core Supply Voltage | — | 1.5 V |
| Maximum Internal Clock | — | 420.17 MHz (per datasheet) |
| Logic Family | — | CMOS |
| Device Type | — | FPGA (Field Programmable Gate Array) |
| Total Pins | — | 672 (FBGA) |
| Type de mémoire | — | TriMatrix embedded block RAM + distributed RAM |