EP1SGX40FF1020I6 vs EP1SGX40FF1020C7 Comparaison
Comparaison détaillée côte à côte de EP1SGX40FF1020I6 par Altera et EP1SGX40FF1020C7 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EP1SGX40FF1020C7 - Stratix GX FPGA 41,250 LE | Intel | 1020-BGA
EP1SGX40FF1020C7 ⚠ Dernier achatComparaison des spécifications
| Paramètre | EP1SGX40FF1020I6 | EP1SGX40FF1020C7 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Dernier achat |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $950,00 | $750,00 |
| Series | Stratix® GX | Stratix GX |
| Family | EP1SGX40 | Stratix GX (EP1SGX40) |
| Logic Elements | 41,250 | — |
| Embedded Memory | 3,423,744 bits | — |
| User I/Os | 624 | — |
| Logic Array Blocks (LABs) | 41,250 | — |
| Boîtier | 1020-ball FineLine BGA | 1020-ball FC-FBGA (S-PBGA-B1020) |
| Type de montage | Surface Mount | Surface Mount |
| Core Voltage (VCCINT) | 1.5 V ±0.15 V | — |
| Température de fonctionnement | -40 °C to +100 °C (Industrial) | 0 °C to 85 °C (commercial) |
| Temperature Grade | I (Industrial) | — |
| Transceiver Channels | Up to 20 channels | 20 full-duplex 3.1875 Gbps + 14 dedicated full-duplex 1.25 Gbps |
| Max Transceiver Data Rate | 3.1875 Gbps | — |
| Transceiver Technology | CDR with embedded SERDES | — |
| Process Technology | CMOS | CMOS |
| Configuration | SRAM-based LUT | — |
| Statut RoHS | [DATA_NEEDED: RoHS status] | Compliant |
| Niveau MSL | [DATA_NEEDED: MSL level] | — |
| Logic Elements (LE) | — | 41,250 |
| Configurable Logic Blocks (CLB) | — | 4,125 |
| Embedded Memory (bits) | — | 3,423,744 |
| User I/O Pins | — | 624 |
| Number of Logic Array Blocks (LAB) | — | 4,125 |
| Number of I/O Banks | — | 12 |
| Core Supply Voltage (VCCINT) | — | 1.425 V to 1.575 V (nominal 1.5 V) |
| Speed Grade | — | 7 (-7, mid-speed) |
| Package Dimensions | — | 33 mm × 33 mm |
| Ball Pitch | — | 1.00 mm |
| Configuration Modes | — | PS, PPS, PPA, JTAG, AS |
| DSP Blocks (9-bit) | — | 176 |
| PLLs | — | 8 enhanced + per-transceiver PLLs |