EP20K100QC240-3 vs EP20K100QC240-1XV Comparaison
Comparaison détaillée côte à côte de EP20K100QC240-3 par Altera et EP20K100QC240-1XV par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Intel
EP20K100QC240-1XV - APEX 20K 100K-Gate FPGA, 240-PQFP | Intel / Altera
EP20K100QC240-1XV ObsoleteComparaison des spécifications
| Paramètre | EP20K100QC240-3 | EP20K100QC240-1XV |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $24,50 | $52,10 |
| Manufacturer | Altera | — |
| FPGA Family | APEX-20K | — |
| Number of Logic Elements | 4160 cells | — |
| Total RAM Bits | 53248 bits | — |
| Number of User I/O | 189 | — |
| Typical Gate Count | 263000 gates | — |
| Core Supply Voltage | 2.5 V | — |
| Fréquence d'horloge maximale | 167 MHz (family rating) | — |
| Speed Grade | -3 | — |
| Technology Process | 0.22 um | — |
| Package Type | 240-BFQFP | — |
| Nombre de broches | 240 | — |
| Type de montage | Surface Mount | Surface Mount (gull-wing leads) |
| Plage de température de fonctionnement | 0 °C to +85 °C (commercial) | — |
| Propagation Delay | [DATA_NEEDED: propagation delay timing table] | — |
| Supported I/O Standards | [DATA_NEEDED: supported I/O standards] | — |
| Configuration / JTAG Interface | [DATA_NEEDED: configuration and JTAG interface details] | — |
| RoHS Compliance | [DATA_NEEDED: RoHS compliance for non-N version] | — |
| Series | — | APEX 20K |
| Device Family | — | APEX 20K (MultiCore architecture) |
| System Gates | — | 100,000 gates |
| Logic Elements (Cells) | — | 4,160 |
| Embedded Memory | — | 53,248 bits |
| User I/Os | — | 189 |
| Dedicated Inputs | — | 4 |
| PLLs | — | 4 |
| Core Supply Voltage (VCCINT) | — | 2.5 V nominal (2.375 V to 2.625 V) |
| I/O Supply Voltage (VCCIO) | — | 3.3 V / 5 V tolerant |
| Propagation Delay (tpd) | — | 2.5 ns |
| Maximum Internal Frequency | — | 250 MHz |
| Process Technology | — | 0.22 um CMOS |
| Boîtier | — | 240-pin PQFP (32 x 32 mm, 0.5 mm pitch) |
| Température de fonctionnement | — | 0C to +85C (commercial) / -40C to +85C (industrial variant) |
| Configuration Interface | — | JTAG / serial (EPC configuration device) |
| Statut RoHS | — | Non-compliant (legacy PQFP, non-LEAD-FREE process) |
| Statut du cycle de vie | — | Obsolete / last-time-buy per Altera PCN |