EP20K100QC240-3N vs EP20K100QC240-1XV Comparaison
Comparaison détaillée côte à côte de EP20K100QC240-3N par Altera et EP20K100QC240-1XV par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Intel
EP20K100QC240-1XV - APEX 20K 100K-Gate FPGA, 240-PQFP | Intel / Altera
EP20K100QC240-1XV ObsoleteComparaison des spécifications
| Paramètre | EP20K100QC240-3N | EP20K100QC240-1XV |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $0,00 | $52,10 |
| Device Type | FPGA | — |
| Family | APEX-20K | — |
| Gate Count | 100000 gates | — |
| Logic Cells | 4160 cells | — |
| User I/O | 189 I/O | — |
| Distributed Memory | 53248 bits | — |
| Macrocells | 416 macrocells | — |
| Tension d'alimentation | 2.375 V to 2.625 V | — |
| Nominal Supply | 2.5 V | — |
| Maximum Frequency | 167 MHz | — |
| Température de fonctionnement | 0 C to 85 C | 0C to +85C (commercial) / -40C to +85C (industrial variant) |
| Boîtier | 240-BFQFP | 240-pin PQFP (32 x 32 mm, 0.5 mm pitch) |
| Nombre de broches | 240 pins | — |
| Type de montage | Surface Mount | Surface Mount (gull-wing leads) |
| Fabrication Process | 0.15 um all-layer copper-metal process | — |
| Package Pitch | 1.27 mm | — |
| Package Dimensions | 45 mm x 45 mm | — |
| Statut RoHS | unknown | Non-compliant (legacy PQFP, non-LEAD-FREE process) |
| AEC-Q100 | not_qualified | — |
| Series | — | APEX 20K |
| Device Family | — | APEX 20K (MultiCore architecture) |
| System Gates | — | 100,000 gates |
| Logic Elements (Cells) | — | 4,160 |
| Embedded Memory | — | 53,248 bits |
| User I/Os | — | 189 |
| Dedicated Inputs | — | 4 |
| PLLs | — | 4 |
| Core Supply Voltage (VCCINT) | — | 2.5 V nominal (2.375 V to 2.625 V) |
| I/O Supply Voltage (VCCIO) | — | 3.3 V / 5 V tolerant |
| Propagation Delay (tpd) | — | 2.5 ns |
| Maximum Internal Frequency | — | 250 MHz |
| Process Technology | — | 0.22 um CMOS |
| Configuration Interface | — | JTAG / serial (EPC configuration device) |
| Statut du cycle de vie | — | Obsolete / last-time-buy per Altera PCN |