EP20K100QC240-3N vs EP20K100QC240-1XV 对比

详细并排对比 EP20K100QC240-3N 出自 Altera 和 EP20K100QC240-1XV 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP20K100QC240-3N EP20K100QC240-1XV
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 有效 Obsolete
库存状态 有库存 有库存
单价(USD) $0.00 $52.10
Device Type FPGA —
Family APEX-20K —
Gate Count 100000 gates —
Logic Cells 4160 cells —
User I/O 189 I/O —
Distributed Memory 53248 bits —
Macrocells 416 macrocells —
电源电压 2.375 V to 2.625 V —
Nominal Supply 2.5 V —
Maximum Frequency 167 MHz —
工作温度 0 C to 85 C 0C to +85C (commercial) / -40C to +85C (industrial variant)
封装 240-BFQFP 240-pin PQFP (32 x 32 mm, 0.5 mm pitch)
引脚数量 240 pins —
安装类型 Surface Mount Surface Mount (gull-wing leads)
Fabrication Process 0.15 um all-layer copper-metal process —
Package Pitch 1.27 mm —
Package Dimensions 45 mm x 45 mm —
RoHS 状态 unknown Non-compliant (legacy PQFP, non-LEAD-FREE process)
AEC-Q100 not_qualified —
Series — APEX 20K
Device Family — APEX 20K (MultiCore architecture)
System Gates — 100,000 gates
Logic Elements (Cells) — 4,160
Embedded Memory — 53,248 bits
User I/Os — 189
Dedicated Inputs — 4
PLLs — 4
Core Supply Voltage (VCCINT) — 2.5 V nominal (2.375 V to 2.625 V)
I/O Supply Voltage (VCCIO) — 3.3 V / 5 V tolerant
Propagation Delay (tpd) — 2.5 ns
Maximum Internal Frequency — 250 MHz
Process Technology — 0.22 um CMOS
Configuration Interface — JTAG / serial (EPC configuration device)
生命周期状态 — Obsolete / last-time-buy per Altera PCN

数据手册与资源

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