EP20K200CF484C8N vs EP20K200CF484C9N Comparaison
Comparaison détaillée côte à côte de EP20K200CF484C8N par Intel et EP20K200CF484C9N par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP20K200CF484C8N | EP20K200CF484C9N |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $102,95 | $201,04 |
| Family | APEX 20KC | APEX 20KC |
| Logic Elements (LEs) | 8,320 | — |
| System Gates | 200,000 | — |
| Embedded System Memory (Bits) | 106,496 | — |
| Maximum Operating Frequency | 301.21 MHz | — |
| Process Technology | 0.15 µm CMOS | 0.15 um CMOS |
| Core Supply Voltage (VCCINT) | 1.8 V | 1.8 V |
| I/O Supply Voltage (VCCIO) | 2.5 V / 3.3 V (MultiVolt) | 3.3 V / 2.5 V / 1.8 V / 1.5 V (MultiVolt) |
| Boîtier | 484-ball FBGA (FineLine BGA) | 484-pin FineLine BGA (FBGA) |
| Speed Grade | -8 | C9 (250 MHz) |
| Operating Temperature (Commercial) | 0 °C to +85 °C | — |
| Lead-Free / Pb-Free | Yes (suffix 'N') | — |
| Number of I/O Pins | [DATA_NEEDED: max user I/O count for FBGA-484 package] | — |
| Configuration Method | JTAG / Serial / Passive Parallel | — |
| Embedded Memory Type | True dual-port / single-port RAM (ESB) | — |
| PLL Count | [DATA_NEEDED: PLL count for EP20K200 family] | — |
| Type de montage | Surface Mount (BGA) | Surface Mount (BGA) |
| Statut RoHS | Compliant (Pb-free suffix) | Compliant |
| Device Type | — | FPGA (Field-Programmable Gate Array) |
| Typical Gates | — | 200,000 |
| Logic Elements | — | 8,320 |
| Embedded System Block (ESB) Bits | — | 106,496 |
| Maximum User I/O | — | 376 |
| Fréquence d'horloge maximale | — | 250 MHz |
| Temperature Grade | — | Industrial (0C to +85C) |
| Configuration Scheme | — | SRAM-based, supports passive serial/parallel and JTAG |
| Niveau MSL | — | 3 (per JEDEC J-STD-020) |