EP20K400CF672C-8 vs EP20K600CF672C-8 Comparaison
Comparaison détaillée côte à côte de EP20K400CF672C-8 par Altera et EP20K600CF672C-8 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EP20K600CF672C-8 - APEX 20KC FPGA 600K Gates 24320 LEs 672-BGA | Intel / Altera
EP20K600CF672C-8 ObsoleteComparaison des spécifications
| Paramètre | EP20K400CF672C-8 | EP20K600CF672C-8 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $95,00 | $1 150,00 |
| Family | APEX 20K | — |
| Logic Elements | 16,640 | — |
| Typical Gates | 400,000 | 600,000 |
| Macros | 1,664 | — |
| Maximum User I/O | 488 | — |
| Number of I/O Banks | [DATA_NEEDED: number of I/O banks] | — |
| Package Type | PBGA-672 (FineLine BGA, 27 x 27 mm, 1.0 mm pitch) | 672-BGA (FineLine BGA, 1.27 mm pitch, 45 x 45 mm) |
| Core Voltage (VCCINT) | 1.8 V nominal (1.71 V to 1.89 V) | — |
| I/O Voltage (VCCIO) | [DATA_NEEDED: VCCIO options] | — |
| Pin-to-Pin Delay (tPD) | 1.78 ns (speed grade -8) | — |
| Speed Grade | -8 | -8 |
| Temperature Grade (C) | Commercial, 0 °C to 85 °C | — |
| Process Technology | 0.15 µm all-layer copper CMOS | 0.15 micrometer all-layer copper-metal |
| Embedded Memory Type | ESB (RAM / ROM / CAM) | — |
| Configuration Interface | JTAG (IEEE 1149.1), Passive Serial, Passive Parallel | — |
| JTAG Support | Yes (IEEE 1149.1 boundary-scan) | — |
| Type de montage | Surface Mount (BGA) | — |
| Statut RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS status] |
| Niveau MSL | [DATA_NEEDED: MSL level] | — |
| Series | — | APEX 20KC |
| Device Type | — | FPGA (Field Programmable Gate Array) |
| Logic Elements (LEs) | — | 24,320 |
| Embedded Memory Bits | — | 311,296 |
| Maximum User I/Os | — | 508 |
| Nombre de broches | — | 672 |
| Propagation Delay (tPD) | — | 1.48 ns |
| Architecture | — | MultiCore (LUT logic + embedded memory) |
| Plage de température de fonctionnement | — | 0C to +85C (commercial) |
| Tension d'alimentation | — | Multi-rail (core + I/O banks) |
| Configuration Method | — | Serial / parallel / JTAG |
| Pin Compatibility | — | Pin-compatible with APEX 20KE family |