EP20K400CF672C-8 vs EP20K600CF672C-8 对比

详细并排对比 EP20K400CF672C-8 出自 Altera 和 EP20K600CF672C-8 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP20K400CF672C-8 EP20K600CF672C-8
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $95.00 $1,150.00
Family APEX 20K —
Logic Elements 16,640 —
Typical Gates 400,000 600,000
Macros 1,664 —
Maximum User I/O 488 —
Number of I/O Banks [DATA_NEEDED: number of I/O banks] —
Package Type PBGA-672 (FineLine BGA, 27 x 27 mm, 1.0 mm pitch) 672-BGA (FineLine BGA, 1.27 mm pitch, 45 x 45 mm)
Core Voltage (VCCINT) 1.8 V nominal (1.71 V to 1.89 V) —
I/O Voltage (VCCIO) [DATA_NEEDED: VCCIO options] —
Pin-to-Pin Delay (tPD) 1.78 ns (speed grade -8) —
Speed Grade -8 -8
Temperature Grade (C) Commercial, 0 °C to 85 °C —
Process Technology 0.15 µm all-layer copper CMOS 0.15 micrometer all-layer copper-metal
Embedded Memory Type ESB (RAM / ROM / CAM) —
Configuration Interface JTAG (IEEE 1149.1), Passive Serial, Passive Parallel —
JTAG Support Yes (IEEE 1149.1 boundary-scan) —
安装类型 Surface Mount (BGA) —
RoHS 状态 [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: RoHS status]
MSL 等级 [DATA_NEEDED: MSL level] —
Series — APEX 20KC
Device Type — FPGA (Field Programmable Gate Array)
Logic Elements (LEs) — 24,320
Embedded Memory Bits — 311,296
Maximum User I/Os — 508
引脚数 — 672
Propagation Delay (tPD) — 1.48 ns
Architecture — MultiCore (LUT logic + embedded memory)
工作温度范围 — 0C to +85C (commercial)
电源电压 — Multi-rail (core + I/O banks)
Configuration Method — Serial / parallel / JTAG
Pin Compatibility — Pin-compatible with APEX 20KE family

数据手册与资源

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