EP20K400FI672-2N vs EP20K400FI672-2X Comparaison
Comparaison détaillée côte à côte de EP20K400FI672-2N par Altera et EP20K400FI672-2X par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP20K400FI672-2N | EP20K400FI672-2X |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | NRND | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $188,75 | $171,00 |
| Family | APEX 20K | APEX 20K |
| Typical Gates | 400,000 | 400,000 system gates |
| Logic Elements / Cells | 16,640 | — |
| Maximum User I/O | 488 | — |
| Embedded Memory Bits | 212,992 bits | — |
| Embedded Array Blocks (EABs) | [DATA_NEEDED: EAB count per family datasheet] | — |
| Process Technology | 0.22 µm CMOS | 0.18 um CMOS, 6-metal |
| Core Voltage | 2.5 V | 1.8 V |
| Maximum Frequency | 200 MHz | — |
| Boîtier | 672-pin FC-FBGA (Flip-Chip Fine-pitch BGA) | 672-ball BGA (FI672) |
| Package Body Size | 27 x 27 mm | — |
| Terminal Pitch | 1.0 mm | — |
| Propagation Delay | 3.1 ns | — |
| Speed Grade | -2 | -2X |
| Température de fonctionnement | Commercial (0 °C to +70 °C) [DATA_NEEDED: industrial variant] | -40C to +85C (industrial) |
| Niveau de sensibilité à l'humidité (MSL) | 3 | — |
| Peak Reflow Temperature | 220 °C | — |
| Type de montage | Surface Mount | — |
| Statut RoHS | Compliant (lead-free) | [DATA_NEEDED: RoHS compliance] |
| Configuration Modes | PS, PPS, PPA, JTAG | — |
| Supported I/O Standards | LVTTL, LVCMOS, SSTL, HSTL | — |
| Logic Elements | — | 16,640 |
| Embedded Memory | — | 212,992 bits |
| User I/O Pins | — | 496 |
| Package Code | — | BGA |
| Terminal Form | — | Ball |
| No. of Terminals | — | 672 |
| Package Shape | — | Square |
| I/O Voltage Support | — | 1.8V / 2.5V / 3.3V / 5V (MultiVolt) |
| Configuration Method | — | SRAM (serial EPROM or JTAG) |
| JTAG Support | — | Yes (IEEE 1149.1) |