EP20K400FI672-3 vs EP20K400FI672-3V Comparaison
Comparaison détaillée côte à côte de EP20K400FI672-3 par Altera et EP20K400FI672-3V par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP20K400FI672-3 | EP20K400FI672-3V |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $195,00 | $285,00 |
| Family | APEX 20K | APEX 20K (EP20K400) |
| Series | EP20K400 | — |
| Logic Elements | 16640 | 16,640 |
| Total Gates | up to 400000 | — |
| Embedded RAM | 212992 bits | — |
| Maximum User I/O | 502 | 502 |
| Dedicated Inputs | 6 | 6 |
| Propagation Delay | 3.6 ns | — |
| Fréquence d'horloge maximale | 833 MHz | 714.2 MHz |
| Supply Voltage (Nominal) | 2.5 V | — |
| Supply Voltage Range | 2.375 V to 2.625 V | — |
| Process Technology | CMOS | 0.18 µm CMOS, 4 metal layers |
| Package Type | PBGA (Plastic BGA) | — |
| Package Code | S-PBGA-B672 | — |
| Terminal Count | 672 | — |
| Terminal Pitch | 1.000 mm | — |
| Package Shape | Square BGA | — |
| Type de montage | Surface Mount | Surface Mount |
| Configuration Interface | JTAG (IEEE 1149.1) | — |
| Température de fonctionnement | [DATA_NEEDED: operating temperature range] | -40 °C to +85 °C (industrial) |
| Niveau MSL | 3 | [DATA_NEEDED: MSL rating] |
| Peak Reflow Temperature | 220 C | — |
| Maximum Gates | — | 400,000 |
| Typical Gates | — | [DATA_NEEDED: typical gates value] |
| Embedded Memory (bits) | — | 212,992 |
| Total User I/O + Dedicated Inputs | — | 496 + 6 (variant dependent) |
| Speed Grade | — | -3 (faster) |
| Core Voltage (VCCINT) | — | 2.5 V nominal (2.375 V to 2.625 V) |
| Boîtier | — | 672-ball FineLine BGA (BBGA), 1.0 mm pitch |
| Programmable via JTAG | — | Yes (IEEE 1149.1) |
| Supported I/O Standards | — | LVCMOS, LVTTL, SSTL, GTL+, HSTL |
| Configuration Modes | — | JTAG, passive serial, passive parallel |
| Statut RoHS | — | [DATA_NEEDED: RoHS status] |