EP20K400FI672-3 vs EP20K400FI672-3V 对比

详细并排对比 EP20K400FI672-3 出自 Altera 和 EP20K400FI672-3V 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP20K400FI672-3 EP20K400FI672-3V
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $195.00 $285.00
Family APEX 20K APEX 20K (EP20K400)
Series EP20K400 —
Logic Elements 16640 16,640
Total Gates up to 400000 —
Embedded RAM 212992 bits —
Maximum User I/O 502 502
Dedicated Inputs 6 6
Propagation Delay 3.6 ns —
最大时钟频率 833 MHz 714.2 MHz
Supply Voltage (Nominal) 2.5 V —
Supply Voltage Range 2.375 V to 2.625 V —
Process Technology CMOS 0.18 µm CMOS, 4 metal layers
Package Type PBGA (Plastic BGA) —
Package Code S-PBGA-B672 —
Terminal Count 672 —
Terminal Pitch 1.000 mm —
Package Shape Square BGA —
安装类型 Surface Mount Surface Mount
Configuration Interface JTAG (IEEE 1149.1) —
工作温度 [DATA_NEEDED: operating temperature range] -40 °C to +85 °C (industrial)
MSL 等级 3 [DATA_NEEDED: MSL rating]
Peak Reflow Temperature 220 C —
Maximum Gates — 400,000
Typical Gates — [DATA_NEEDED: typical gates value]
Embedded Memory (bits) — 212,992
Total User I/O + Dedicated Inputs — 496 + 6 (variant dependent)
Speed Grade — -3 (faster)
Core Voltage (VCCINT) — 2.5 V nominal (2.375 V to 2.625 V)
封装 — 672-ball FineLine BGA (BBGA), 1.0 mm pitch
Programmable via JTAG — Yes (IEEE 1149.1)
Supported I/O Standards — LVCMOS, LVTTL, SSTL, GTL+, HSTL
Configuration Modes — JTAG, passive serial, passive parallel
RoHS 状态 — [DATA_NEEDED: RoHS status]

数据手册与资源

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